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78M6612 Single-Phase, Dual-Outlet Power and Energy Measurement IC
Simplifying System IntegrationTM
DATA SHEET
June 2009
DESCRIPTION The Teridian 78M6612 is a highly integrated, single-phase, power and energy measurement and monitoring SOC which includes a 32-bit compute engine (CE), an MPU core, RTC, and Flash. The Teridian patented Single Converter Technology(R) with a 22-bit delta-sigma ADC, 4 analog inputs, digital temperature compensation, and precision voltage reference supports a wide range of single-phase, dual-outlet power measurement applications with very few external components. With measurement technology leveraged from Teridian's flagship utility metering IC's it offers features including 32 KB of Flash program memory, 2 KB shared RAM, three low power modes with internal timer or external event wakeup, 2 UARTs , I2C/Micro wire EEPROM I/F, and an insystem programmable Flash. Complete Outlet Measurement Unit (OMU) and AC Power Monitor (AC-PMON) firmware is available or can be pre-loaded into the IC. A complete array of ICE and development tools, programming libraries and reference designs enable rapid development and certification of Power and Energy Measurement solutions that meet the most demanding worldwide electricity metering standards.
LIVE NEUT CT OUTLET POWER SUPPLY
FEATURES
* Measures each outlet of a duplex receptacle with a single IC * Provides complete energy measurement and communication protocol capability in a single IC * Intelligent switch control capability * < 0.5% Wh accuracy over 2000:1 current range and over temperature * Exceeds IEC62053 / ANSIC12.20 standards * Voltage reference < 40 ppm/C * Four sensor inputs - VDD referenced * Low jitter Wh and VARh pulse test outputs (10 kHz maximum) * Pulse count for pulse outputs * Line frequency count for RTC * Digital temperature compensation * Sag detection for phase A and B * Independent 32-bit compute engine * 46-64 Hz line frequency range with same calibration * Phase compensation (7) * Battery backup for RTC and battery monitor * Three battery modes with wake-up timer: Brownout mode (48 A) LCD mode (5.7 A) Sleep mode (2.9 A) * Energy display on main power failure * Wake-up timer * 22-bit delta-sigma ADC * 8-bit MPU (80515), 1 clock cycle per instruction w/ integrated ICE for MPU debug * RTC with temperature compensation * Auto-Calibration * Hardware watchdog timer, power fail monitor * LCD driver (up to 152 pixels) * Up to 18 general purpose I/O pins * 32 kHz time base * 32 KB Flash with security * 2 KB MPU XRAM * Two UARTs * Digital I/O pins compatible with 5 V inputs * 64-pin LQFP or 68-pin QFN package * RoHS compliant (6/6) lead-free packages * Complete Application Firmware available
CONVERTER IA VA IB VB
V3.3A
V3.3 SYS
GNDA GNDD PWR MODE CONTROL WAKE-UP REGULATOR VBAT V2.5 BATTERY OPTIONAL
TERIDIAN 78M6612
VOLTAGE REF VREF VBIAS SERIAL PORTS TX0 RX0 RX1 TX1 COMPARATOR V1 OSC/PLL XIN XOUT
TEMP SENSOR RAM FLASH COMPUTE ENGINE
DIO, PULSE
COM0..3 SEG0..18 SEG 24..31/ DIO 4..11 SEG 34..37/ DIO 14..17 SEG 32,33, 38/ICE
2
OPTIONAL
I C or Wire EEPROM
POWER FAULT 32 kHz
MPU
RTC TIMERS
ICE
ICE_E
V3P3D GNDD
Rev. 1.2
(c) 2009 Teridian Semiconductor Corporation
1
78M6612 Data Sheet
DS_6612_001
Table of Contents
1 Hardware Description ...................................................................................................................8 1.1 Hardware Overview..................................................................................................................8 1.2 Analog Front End (AFE) ..........................................................................................................9 1.2.1 Input Multiplexer ..........................................................................................................9 1.2.2 A/D Converter (ADC) ...................................................................................................9 1.2.3 FIR Filter ...................................................................................................................10 1.2.4 Voltage References ...................................................................................................10 1.2.5 Temperature Sensor ..................................................................................................11 1.2.6 Battery Monitor ..........................................................................................................11 1.2.7 Functional Description ...............................................................................................11 1.3 Digital Computation Engine (CE)...........................................................................................12 1.3.1 Measurement Equations ............................................................................................13 1.3.2 Real-Time Monitor .....................................................................................................13 1.3.3 Pulse Generator ........................................................................................................13 1.3.4 CE Functional Overview.............................................................................................14 1.4 80515 MPU Core ..................................................................................................................16 1.4.1 Memory Organization.................................................................................................17 1.4.2 Special Function Registers (SFRs) ............................................................................19 1.4.3 Special Function Registers (Generic 80515 SFRs) ....................................................20 1.4.4 Special Function Registers Specific to the 78M6612 .................................................22 1.4.5 Instruction Set ...........................................................................................................24 1.4.6 UARTs.......................................................................................................................24 1.4.7 Timers and Counters .................................................................................................27 1.4.8 WD Timer (Software Watchdog Timer).......................................................................29 1.4.9 Interrupts ...................................................................................................................31 1.5 On-Chip Resources ...............................................................................................................40 1.5.1 Oscillator ...................................................................................................................40 1.5.2 PLL and Internal Clocks ............................................................................................40 1.5.3 Real-Time Clock (RTC) ..............................................................................................40 1.5.4 Temperature Sensor ..................................................................................................41 1.5.5 Physical Memory .......................................................................................................41 1.5.6 Optical Interface ........................................................................................................42 1.5.7 Digital I/O ..................................................................................................................43 1.5.8 LCD Drivers ...............................................................................................................45 1.5.9 Battery Monitor ..........................................................................................................45 1.5.10 EEPROM Interface ....................................................................................................46 1.5.11 Hardware Watchdog Timer ........................................................................................49 1.5.12 Program Security .......................................................................................................49 1.5.13 Test Ports ..................................................................................................................50 Functional Description ................................................................................................................51 2.1 Theory of Operation ...............................................................................................................51 2.2 System Timing Summary ......................................................................................................52 2.3 Battery Modes .......................................................................................................................53 2.3.1 BROWNOUT Mode ...................................................................................................54 2.3.2 LCD Mode .................................................................................................................55 2.3.3 SLEEP Mode.............................................................................................................55 2.4 Fault and Reset Behavior ......................................................................................................60 2.5 Wake Up Behavior ................................................................................................................61 2.5.1 Wake on Timer ..........................................................................................................61 2.6 Data Flow ..............................................................................................................................61 2.7 CE/MPU Communication ......................................................................................................62
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78M6612 Data Sheet
Application Information...............................................................................................................63 3.1 Connection of Sensors (CT, Resistive Shunt) ........................................................................63 3.2 Temperature Measurement ...................................................................................................64 3.3 Temperature Compensation ..................................................................................................64 3.4 Temperature Compensation and Mains Frequency Stabilization for the RTC ......................... 65 3.5 Connecting 5V Devices .........................................................................................................66 3.6 Connecting LCDs ..................................................................................................................67 3.7 Connecting I2C EEPROMs ....................................................................................................69 3.8 Connecting 3-Wire EEPROMs ..............................................................................................70 3.9 UART0 (TX/RX) ....................................................................................................................70 3.10 UART1 Interface....................................................................................................................71 3.11 Connecting V1 and Reset Pins .............................................................................................71 3.12 Connecting the Emulator Port Pins .......................................................................................72 3.13 Crystal Oscillator ...................................................................................................................73 3.14 Flash Programming ...............................................................................................................73 3.15 MPU Firmware Library ...........................................................................................................73 3.16 Measurement Calibration.......................................................................................................73 Firmware Interface ......................................................................................................................74 4.1 I/O RAM Map ........................................................................................................................74 4.2 SFR Map (SFRs Specific to Teridian 80515) .........................................................................75 4.3 I/O RAM Description - Alphabetical Order.............................................................................76 4.4 CE Interface Description ........................................................................................................83 4.4.1 CE Program ..............................................................................................................83 4.4.2 Formats .....................................................................................................................83 4.4.3 Constants ..................................................................................................................83 4.4.4 Environment ..............................................................................................................83 4.4.5 CE Calculations .........................................................................................................84 4.4.6 CE Status ..................................................................................................................84 4.4.7 CE Transfer Variables ................................................................................................85 Electrical Specifications .............................................................................................................89 5.1 Absolute Maximum Ratings ...................................................................................................89 5.2 Recommended External Components ...................................................................................90 5.3 Recommended Operating Conditions ....................................................................................90 5.4 Performance Specifications ...................................................................................................91 5.4.1 Input Logic Levels .....................................................................................................91 5.4.2 Output Logic Levels ...................................................................................................91 5.4.3 Power-Fault Comparator ............................................................................................91 5.4.4 Battery Monitor ..........................................................................................................91 5.4.5 Supply Current ..........................................................................................................93 5.4.6 V3P3D Switch ...........................................................................................................93 5.4.7 2.5V Voltage Regulator..............................................................................................93 5.4.8 Low Power Voltage Regulator ....................................................................................93 5.4.9 Crystal Oscillator........................................................................................................95 5.4.10 VREF, VBIAS ............................................................................................................95 5.4.11 LCD Drivers ...............................................................................................................95 5.4.12 ADC Converter, V3P3A Referenced ..........................................................................96 5.4.13 UART1 Interface ........................................................................................................96 5.4.14 Temperature Sensor ..................................................................................................96 5.5 Timing Specifications ............................................................................................................97 5.5.1 RAM and Flash Memory ............................................................................................97 5.5.2 Flash Memory Timing ................................................................................................97 5.5.3 EEPROM Interface ....................................................................................................97 5.5.4 RESET and V1 ..........................................................................................................97 5.5.5 RTC...........................................................................................................................97 3
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DS_6612_001
5.5.6 Typical Performance Data ..........................................................................................98 6 Packaging ..................................................................................................................................100 6.1 64 LQFP Package...............................................................................................................100 6.1.1 Pinout ......................................................................................................................100 6.1.2 Package Outline (LQFP 64).....................................................................................101 6.1.3 Recommended PCB Land Pattern for the LQFP-64 Package .................................. 102 6.2 68-Pin QFN Package ..........................................................................................................103 6.2.1 Pinout ......................................................................................................................103 6.2.2 Package Outline ......................................................................................................104 6.2.3 Recommended PCB Land Pattern for the QFN-68 Package .................................... 105 Pin Descriptions ........................................................................................................................106 7.1 Power/Ground Pins .............................................................................................................106 7.2 Analog Pins.........................................................................................................................106 7.3 Digital Pins ..........................................................................................................................107 I/O Equivalent Circuits...............................................................................................................108 Ordering Information .................................................................................................................109 Related Documentation.............................................................................................................109 Contact Information...................................................................................................................109
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8 9 10 11
Revision History ................................................................................................................................110
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DS_6612_001
78M6612 Data Sheet
Figures
Figure 1: IC Functional Block Diagram ..................................................................................................... 7 Figure 2: General Topology of a Chopped Amplifier ............................................................................... 10 Figure 3: AFE Block Diagram ................................................................................................................ 11 Figure 4: Samples from Multiplexer Cycle .............................................................................................. 14 Figure 5: Accumulation Interval.............................................................................................................. 15 Figure 6: Interrupt Structure................................................................................................................... 39 Figure 7: Optical Interface...................................................................................................................... 42 Figure 8: Connecting an External Load to DIO Pins ............................................................................... 44 Figure 9: 3-Wire Interface. Write Command, HiZ=0 .............................................................................. 47 Figure 10: 3-Wire Interface. Write Command, HiZ=1 ............................................................................ 48 Figure 11: 3-Wire Interface. Read Command ........................................................................................ 48 Figure 12: 3-Wire Interface. Write Command when CNT=0 .................................................................. 48 Figure 13: 3-Wire Interface. Write Command when HiZ=1 and WFR=1 ................................................ 48 Figure 14: Functions Defined by V1 ....................................................................................................... 49 Figure 15: Voltage. Current, Momentary and Accumulated Energy ....................................................... 51 Figure 16: Timing Relationship between ADC MUX, Compute Engine, and Serial Transfers .................. 52 Figure 17: RTM Output Format .............................................................................................................. 52 Figure 18: Operation Modes State Diagram ........................................................................................... 55 Figure 19: Functional Blocks in BROWNOUT Mode (inactive blocks grayed out) ................................... 56 Figure 20: Functional Blocks in LCD Mode (inactive blocks grayed out) ................................................. 57 Figure 21: Functional Blocks in SLEEP Mode (inactive blocks grayed out)............................................. 58 Figure 22: Transition from BROWNOUT to MISSION Mode when System Power Returns ..................... 59 Figure 23: Power-Up Timing with V3P3SYS and VBAT Tied Together ................................................... 59 Figure 24: Power-Up Timing with VBAT Only ......................................................................................... 60 Figure 25: MPU/CE Data Flow ............................................................................................................... 61 Figure 26: MPU/CE Communication ...................................................................................................... 62 Figure 27: Resistive Voltage Divider (Left), Current Transformer (Right) ................................................. 63 Figure 28: Resistive Shunt ..................................................................................................................... 63 Figure 29: Crystal Frequency over Temperature..................................................................................... 65 Figure 30: Crystal Compensation ........................................................................................................... 66 Figure 31: Connecting LCDs ................................................................................................................. 67 Figure 32: I2C EEPROM Connection ..................................................................................................... 70 Figure 33: 3-Wire EEPROM Connection ................................................................................................ 70 Figure 34: Connections for the RX Pin ................................................................................................... 70 Figure 35: Connection for Optical Components ...................................................................................... 71 Figure 36: Voltage Divider for V1 ........................................................................................................... 72 Figure 37: External Components for RESET: Development Circuit (Left), Production Circuit (Right)....... 72 Figure 38: External Components for the Emulator Interface ................................................................... 73 Figure 39: Wh Accuracy, 10 mA to 20 A at 120 V/60 Hz and Room Temperature Using a 4 m Current Shunt ..................................................................................................... 98 Figure 40: Measurement Accuracy over Harmonics at 240 V, 30A per IEC62053-2x Section 8.2.1 ........................................................................................................................... 98 Figure 41: Typical Measurement Accuracy over Temperature Relative to 25C ...................................... 99 Figure 42: 64-Pin LQFP Pinout ........................................................................................................... 100 Figure 43: 68-Pin QFN Pinout ............................................................................................................. 103
Rev. 1.2
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78M6612 Data Sheet
DS_6612_001
Tables
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles....................................................... 9 Table 2: CE DRAM Locations for ADC Results ...................................................................................... 12 Table 3: Memory Map ............................................................................................................................ 17 Table 4: Stretch Memory Cycle Width .................................................................................................... 18 Table 5: Internal Data Memory Map ....................................................................................................... 19 Table 6: Special Function Registers Locations ....................................................................................... 19 Table 7: Special Function Registers Reset Values ................................................................................. 20 Table 8: PSW Register ............................................................................................................................ 21 Table 9: Port Registers .......................................................................................................................... 22 Table 10: Special Function Registers ..................................................................................................... 22 Table 11: Baud Rate Generation ............................................................................................................ 24 Table 12: UART Modes.......................................................................................................................... 24 Table 13: The S0CON Register ............................................................................................................... 25 Table 14: The S1CON Register ............................................................................................................... 26 Table 15: The TCON Register ................................................................................................................ 27 Table 16: The TMOD Register................................................................................................................ 28 Table 17: Timers/Counters Mode Description ......................................................................................... 28 Table 18: Timer Modes .......................................................................................................................... 28 Table 19: The PCON Register ................................................................................................................ 29 Table 20: The IEN0 Register .................................................................................................................. 30 Table 21: The IEN1 Register .................................................................................................................. 30 Table 22: The IP0 Register..................................................................................................................... 30 Table 23: The WDTREL Register ............................................................................................................ 31 Table 24: The IEN0 Register .................................................................................................................. 32 Table 25: The IEN1 Register .................................................................................................................. 32 Table 26: The IEN2 Register .................................................................................................................. 33 Table 27: The TCON Register ................................................................................................................ 33 Table 28: The T2CON Bit Functions ....................................................................................................... 33 Table 29: The IRCON Register ............................................................................................................... 34 Table 30: External MPU Interrupts ......................................................................................................... 34 Table 31: Interrupt Enable and Flag Bits ................................................................................................ 35 Table 32: Priority Level Groups .............................................................................................................. 36 Table 33: The IP0 Register..................................................................................................................... 37 Table 34: The IP1 Register..................................................................................................................... 37 Table 35: Priority Levels ......................................................................................................................... 37 Table 36: Interrupt Polling Sequence ..................................................................................................... 37 Table 37: Interrupt Vectors .................................................................................................................... 38 Table 38: Data/Direction Registers and Internal Resources for DIO Pin Groups ..................................... 43 Table 39: DIO_DIR Control Bit ............................................................................................................... 44 Table 40: Selectable Controls using the DIO_DIR Bits ........................................................................... 45 Table 41: EECTRL Status Bits ................................................................................................................ 46 Table 42: EECTRL Bits for 3-Wire Interface ............................................................................................ 47 Table 43: TMUX[4:0] Selections ............................................................................................................. 50 Table 44: Available Circuit Functions ..................................................................................................... 54 Table 45: Frequency over Temperature.................................................................................................. 65 Table 46: LCD and DIO Pin Assignment by LCD_NUM for the QFN-68 Package ................................... 68 Table 47: LCD and DIO Pin Assignment by LCD_NUM for the LQFP-64 Package ................................. 69 Table 48: I/O RAM Map - In Numerical Order........................................................................................ 74 Table 49: SFR Map - In Numerical Order .............................................................................................. 75 Table 50: I/O RAM Map - Alphabetical Order ........................................................................................ 76
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78M6612 Data Sheet
VREF
V3P3A
GNDA
V3P3SYS
IA VA IB VB
VBAT
ADC CONVERTER MUX VBIAS VBIAS
V3P3D
V3P3A
+ ADC_E FIR VBAT FIR_LEN
V3P3D
TEMP MUX MUX CTRL EQU MUX_ALT CHOP_E MUX_DIV OSC (32KHz)
VREF VREF_CAL VREF_DIS CROSS CK32 VREF
VBAT
VOLT REG
XIN XOUT CKTEST/ SEG19
RTCLK (32KHz)
MCK PLL
CK32 32KHz
DIV ADC
LCD_ONLY SLEEP
GNDD V2P5
CKOUT_E 4.9MHz CKOUT_E CK_GEN ECK_DIS MPU_DIV MUX_SYNC CKCE <4.9MHz STRT CE 32 bit Compute Engine CK_2X
CKADC 4.9MHz
CKFIR 4.9MHz V3P3D LCD_GEN CE RAM (0.5KB) VLC2 VLC1 LCD_MODE LCD_E LCD DISPLAY DRIVER MEMORY SHARE LCD_NUM LCD_MODE LCD_CLK LCD_E LCD_BLKMAP LCD_SEG LCD_Y DIGITAL I/O DIO_EEX DIO_PV/PW DIO_DIR DIO_R LCD_NUM DIO RTC RTC_DEC_SEC RTC_INC_SEC CONFIGURATION PARAMETERS VLC0 2.5V to logic
WPULSE VARPULSE RTM DATA 00-7F
MUX
(SEG13 and SEG 14 on 68 Pin Package Only)
TEST
TEST MODE
COM0..3 SEG0..18
SEG32,33 SEG19,38
CE CONTROL RTM_0..3 RTM_E CE_E
PROG 000-7FF
1000-11FF
SEG24/DIO4 .. SEG31/DIO11 SEG34/DIO14 .. SEG37/DIO17, SEG39/DIO19, SEG40/DIO20
XFER BUSY
CE_BUSY
I/O RAM
PLS_INV PLS_INTERVAL PLS_MAXWIDTH CE_LCTN EQU PRE_SAMPS SUM_CYCLES
WPULSE VARPULSE EEPROM INTERFACE
DIO1,2
RTCLK
CKMPU <4.9MHz SDCK SDOUT UART SDIN MPU (80515) DATA 0000-FFFF 0000-07FF 2000-20FF
RX TX
RX1/ DIO1
OPTICAL
CONFIG
(68 Pin Package Only)
DIO3, DIO21/SEG41
MPU XRAM (2KB)
TX1/ DIO2/ WPULSE/ VARPULSE
MOD OPT_TXMOD OPT_FDC VBIAS
OPT_RXDIS OPT_RXINV OPT_TXE OPT_TXINV
PROG 0000-7FFF
MEMORY SHARE CE_LCTN
00007FFF
FLASH (32KB) FLSH66ZT
MPU_RSTZ POWER FAULT WAKE FAULTZ COMP_STAT
V1
EMULATOR PORT E_RXTX E_TCLK E_RST (Open Drain) TEST MUX TMUX[4:0]
TMUXOUT
RESET
E_RXTX/SEG38 E_TCLK/SEG33 E_RST/SEG32
ICE_E
January 14, 2009
Figure 1: IC Functional Block Diagram
Rev. 1.2
7
78M6612 Data Sheet
DS_6612_001
1 Hardware Description
1.1 Hardware Overview
The Teridian 78M6612 single-chip measurement unit integrates all primary functional blocks required to implement a solid-state electricity Power and Energy Measurement function. Included on chips are: * * * * * * * * * An analog front end (AFE) An independent digital computation engine (CE) An 8051-compatible microprocessor (MPU) which executes one instruction per clock cycle (80515) A voltage reference A temperature sensor LCD drivers RAM and Flash memory A real time clock (RTC) A variety of I/O pins
Various current sensor technologies are supported including Current Transformers (CT), and Resistive Shunts. In a typical application, the 32-bit compute engine (CE) of the 78M6612 sequentially processes the samples from the voltage inputs on pins IA, VA, IB, VB and performs calculations to measure active energy (Wh), reactive energy (VARh), A2h, and V2h for four-quadrant measurement. These measurements are then accessed by the MPU, processed further and output using the peripheral devices available to the MPU. In addition to advanced measurement functions, the real time clock function allows the 78M6612 to record time of use (TOU) measurement information for multi-rate applications and to time-stamp events. Measurements can be displayed on 3.3 V LCDs if desired. Flexible mapping of LCD display segments will facilitate utilization of existing custom LCDs. Design trade-off between number of LCD segments vs. DIO pins can be implemented in software to accommodate various requirements. In addition to the temperature-trimmed ultra-precision voltage reference, the on-chip digital temperature compensation mechanism includes a temperature sensor and associated controls for correction of unwanted temperature effects on measurement and RTC accuracy, e.g. to meet the requirements of ANSI and IEC standards. Temperature dependent external components such as crystal oscillator, current transformers (CTs), and their corresponding signal conditioning circuits can be characterized and their correction factors can be programmed to produce measurements with exceptional accuracy over the industrial temperature range, if desired. One of the two internal UARTs is adapted to support an Infrared LED with internal drive and sense configuration, and can also function as a standard UART. The optical output can be modulated at 38 kHz. A block diagram of the IC is shown in Figure 1. A detailed description of various functional blocks follows.
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78M6612 Data Sheet
1.2
Analog Front End (AFE)
The AFE of the 78M6612 is comprised of an input multiplexer, a delta-sigma A/D converter and a voltage reference.
1.2.1 Input Multiplexer
The input multiplexer supports up to four input signals that are applied to pins IA, VA, IB and VB of the device. Additionally, using the alternate mux selection, it has the ability to select temperature and the battery voltage. The multiplexer can be operated in two modes: * * During a normal multiplexer cycle, the signals from the IA, IB, VA, and VB pins are selected. During the alternate multiplexer cycle, the temperature signal (TEMP) and the battery monitor are selected, along with the signal sources shown in Table 1. To prevent unnecessary drainage on the battery, the battery monitor is enabled only with the BME bit (0x2020[6]) in the I/O RAM.
The alternate mux cycles are usually performed infrequently (e.g. every second) by the MPU. In order to prevent disruption of the voltage tracking PLL and voltage allpass networks, VA is not replaced in the ALT mux selections. Table 1 details the regular and alternative MUX sequences. Missing samples due to an ALT multiplexer sequence are filled in by the CE. Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles Regular MUX Sequence Mux State EQU 2 0 IA 1 VA 2 IB 3 VB 0 TEMP ALT MUX Sequence Mux State 1 VA 2 IB 3 VBAT
In a typical application, IA and IB are connected to current sensors that sense the current on each branch of the line voltage. VA and VB are typically connected to voltage sensors through resistor dividers. The multiplexer control circuit handles the setting of the multiplexer. The function of the control circuit is governed by the I/O RAM registers MUX_ALT, MUX_DIV and EQU. MUX_DIV controls the number of samples per cycle. It can request 2, 3, or 4 multiplexer states per cycle. Multiplexer states above 4 are reserved and must not be used. The multiplexer always starts at the beginning of its list and proceeds until MUX_DIV states have been converted. The MUX_ALT bit requests an alternative multiplexer frame. The bit may be asserted on any MPU cycle and may be subsequently de-asserted on any cycle including the next one. A rising edge on MUX_ALT will cause the multiplexer control circuit to wait until the next multiplexer cycle and implement a single alternate cycle. The multiplexer control circuit also controls the FIR filter initiation and the chopping of the ADC reference voltage, VREF. The multiplexer control circuit is clocked by CK32, the 32768 Hz clock from the PLL block, and launches with each new pass of the CE program.
1.2.2 A/D Converter (ADC)
A single delta-sigma A/D converter digitizes the voltage and current inputs to the 78M6612. The resolution of the ADC is programmable using the FIR_LEN register as shown in Section 4.3 I/O RAM Description. ADC resolution can be selected to be 21 bits (FIR_LEN=0), or 22 bits (FIR_LEN=1). Conversion time is two cycles of CK32 with FIR_LEN = 0 and three cycles with FIR_LEN = 1. In order to provide the maximum resolution, the ADC should be operated with FIR_LEN = 1. Accuracy and timing specifications in this data sheet are based on FIR_LEN = 1. Rev. 1.2 9
78M6612 Data Sheet
DS_6612_001
Initiation of each ADC conversion is controlled by the multiplexer control circuit as described previously. At the end of each ADC conversion, the FIR filter output data is stored into the CE DRAM location determined by the multiplexer selection.
1.2.3 FIR Filter
The finite impulse response filter is an integral part of the ADC and it is optimized for use with the multiplexer. The purpose of the FIR filter is to decimate the ADC output to the desired resolution. At the end of each ADC conversion, the output data is stored into the fixed CE DRAM location determined by the multiplexer selection. FIR data is stored LSB justified, but shifted left by nine bits.
1.2.4 Voltage References
The device includes an on-chip precision bandgap voltage reference that incorporates auto-zero techniques. The reference is trimmed to minimize errors caused by component mismatch and drift. The result is a voltage output with a predictable temperature coefficient. The amplifier within the reference is chopper stabilized, i.e. the polarity can be switched by the MPU using the I/O RAM register CHOP_E (0x2002[5:4]). The two bits in the CHOP_E register enable the MPU to operate the chopper circuit in regular or inverted operation, or in "toggling" mode. When the chopper circuit is toggled in between multiplexer cycles, DC offsets on the measured signals will automatically be averaged out. The general topology of a chopped amplifier is given in Figure 2.
A B A
Vinp Vinn CROSS
+ G -
Voutp Voutn
B A B
A B
Figure 2: General Topology of a Chopped Amplifier It is assumed that an offset voltage Voff appears at the positive amplifier input. With all switches, as controlled by CROSS in the "A" position, the output voltage is: Voutp - Voutn = G (Vinp + Voff - Vinn) = G (Vinp - Vinn) + G Voff With all switches set to the "B" position by applying the inverted CROSS signal, the output voltage is: Voutn - Voutp = G (Vinn - Vinp + Voff) = G (Vinn - Vinp) + G Voff, or Voutp - Voutn = G (Vinp - Vinn) - G Voff Thus, when CROSS is toggled, e.g. after each multiplexer cycle, the offset will alternately appear on the output as positive and negative, which results in the offset effectively being eliminated, regardless of its polarity or magnitude. When CROSS is high, the hookup of the amplifier input devices is reversed. This preserves the overall polarity of that amplifier gain, it inverts its input offset. By alternately reversing the connection, the amplifier's offset is averaged to zero. This removes the most significant long-term drift mechanism in the voltage reference. The CHOP_E bits control the behavior of CROSS. The CROSS signal will reverse the amplifier connection in the voltage reference in order to negate the effects of its offset. On the first CK32 10 Rev. 1.2
DS_6612_001
78M6612 Data Sheet
rising edge after the last mux state of its sequence, the mux will wait one additional CK32 cycle before beginning a new frame. At the beginning of this cycle, the value of CROSS will be updated according to the CHOP_E bits. The extra CK32 cycle allows time for the chopped VREF to settle. During this cycle, MUXSYNC is held high. The leading edge of muxsync initiates a pass through the CE program sequence. The beginning of the sequence is the serial readout of the four RTM words. CHOP_E has 3 states: positive, reverse, and chop. In the positive state, CROSS is held low. In the reverse state, CROSS is held high. In the chop state, CROSS is toggled near the end of each Mux Frame, as described above. It is desirable that CROSS take on alternate values at the beginning of each Mux cycle. For this reason, if chop state is selected, CROSS will not toggle at the end of the last Mux cycle in a SUM cycle. The internal bias voltage VBIAS (typically 1.6 V) is used by the ADC when measuring the temperature and battery monitor signals.
1.2.5 Temperature Sensor
The 78M6612 includes an on-chip temperature sensor implemented as a bandgap reference. It is used to determine the die temperature The MPU may request an alternate multiplexer cycle containing the temperature sensor output by asserting MUX_ALT. The primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system (see Section 3.3 Temperature Compensation).
1.2.6 Battery Monitor
The battery voltage is measured by the ADC during alternative multiplexer frames if the BME (Battery Measure Enable) bit in the I/O RAM is set. While BME is set, an on-chip 45 k load resistor is applied to the battery, and a scaled fraction of the battery voltage is applied to the ADC input. After each alternative MUX frame, the result of the ADC conversion is available at CE DRAM address 07. BME is ignored and assumed zero when system power is not available (V1 < VBIAS). See Section 5.4.4 Battery Monitor for details regarding the ADC LSB size and the conversion accuracy.
1.2.7 Functional Description
The AFE functions as a data acquisition system, controlled by the MPU. The main signals (IA, VA, IB, VB) are sampled and the ADC counts obtained are stored in CE DRAM where they can be accessed by the CE and, if necessary, by the MPU. Alternate multiplexer cycles are initiated less frequently by the MPU to gather access to the slow temperature and battery signals.
VREF
IA VA IB VB
VBAT
ADC CONVERTER MUX VBIAS VBIAS
V3P3A
+ ADC_E FIR
TEMP MUX MUX CTRL EQU MUX_ALT CHOP_E MUX_DIV
VREF VREF_CAL VREF_DIS CROSS CK32 FIR_DONE FIR_START VREF FIR_LEN
4.9MHz
Figure 3: AFE Block Diagram
Rev. 1.2
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78M6612 Data Sheet
DS_6612_001
1.3
Digital Computation Engine (CE)
The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to accurately measure energy. The CE calculations and processes include: * * * * * * * Multiplication of each current sample with its associated voltage sample to obtain the energy per sample (when multiplied with the constant sample time). Frequency-insensitive delay cancellation on all four channels (to compensate for the delay between samples caused by the multiplexing scheme). 90 phase shifter (for VAR calculations). Pulse generation. Monitoring of the input signal frequency (for frequency and phase information). Monitoring of the input signal amplitude (for sag detection). Scaling of the processed samples based on calibration coefficients. CE code is provided by Teridian as a part of the application firmware available. The CE is not programmable by the user. Measurement algorithms in the CE code can be customized by Teridian upon request. The CE program resides in Flash memory. Common access to Flash memory by CE and MPU is controlled by a memory share circuit. Each CE instruction word is two bytes long. Allocated Flash space for the CE program cannot exceed 1024 words (2 KB). The CE program counter begins a pass through the CE code each time multiplexer state 0 begins. The code pass ends when a HALT instruction is executed. For proper operation, the code pass must be completed before the multiplexer cycle ends (see Section 2.2 System Timing Summary). The CE program must begin on a 1 Kbyte boundary of the Flash address. The I/O RAM register CE_LCTN[4:0] defines which 1 KB boundary contains the CE code. Thus, the first CE instruction is located at 1024*CE_LCTN[4:0]. The CE DRAM can be accessed by the FIR filter block, the RTM circuit, the CE, and the MPU. Assigned time slots are reserved for FIR, RTM, and MPU, respectively, to prevent bus contention for CE DRAM data access. Holding registers are used to convert 8-bit wide MPU data to/from 32-bit wide CE DRAM data, and wait states are inserted as needed, depending on the frequency of CKMPU. The CE DRAM contains 128 32-bit words. The MPU can read and write the CE DRAM as the primary means of data communication between the two processors. Table 2 shows the CE DRAM addresses allocated to analog inputs from the AFE. Table 2: CE DRAM Locations for ADC Results Address (Hex) 1000 1004 1008 100C 1010 1014 1018 101C 12 Name IA VA IB VB - - TEMP VBAT Description Branch A current A voltage Branch B current B voltage Not used Not used Temperature Battery voltage Rev. 1.2
DS_6612_001
78M6612 Data Sheet
The CE of the 78M6612 is aided by support hardware that facilitates implementation of equations, pulse counters, and accumulators. This support hardware is controlled through I/O RAM locations EQU (equation assist), DIO_PV and DIO_PW (pulse count assist), and PRE_SAMPS and SUM_CYCLES (accumulation assist). PRE_SAMPS and SUM_CYCLES support a dual level accumulation scheme where the first accumulator accumulates results from PRE_SAMPS samples and the second accumulator accumulates up to SUM_CYCLES of the first accumulator results. The integration time for each energy output is PRE_SAMPS * SUM_CYCLES/2520.6 (with MUX_DIV = 01). CE hardware issues the XFER_BUSY interrupt when the accumulation is complete.
1.3.1 Measurement Equations
Refer to the applicable 78M6612 Firmware Description Document for further details.
1.3.2 Real-Time Monitor
The CE contains a Real-Time Monitor (RTM), which can be programmed through the UART to monitor four selectable CE DRAM locations at full sample rate for system debug purposes. The four monitored locations are serially output to the TMUXOUT pin via the digital output multiplexer at the beginning of each CE code pass. The RTM can be enabled and disabled with RTM_EN. The RTM output is clocked by CKTEST. Each RTM word is clocked out in 35 cycles and contains a leading flag bit. See Section 2 Functional Description for the RTM output format. RTM is low when not in use.
1.3.3 Pulse Generator
The chip contains two pulse generators that create low-jitter pulses at a rate set by either CE or MPU for calibration purposes. The function is distinguished by EXT_PULSE (a CE input variable in CE DRAM): * * If EXT_PULSE = 1, APULSEW*WRATE and APULSER*WRATE control the pulse rate (external pulse generation). If EXT_PULSE is 0, APULSEW is replaced with WSUM_X and APULSER is replaced with VARSUM_X (internal pulse generation).
The I/O RAM bits DIO_PV and DIO_PW, as described in Section 1.5.7 Digital I/O, can be programmed to route WPULSE to the output pin DIO6 and VARPULSE to the output pin DIO7. Pulses can also be output on TX1 (see TX1E[1:0] for details). During each CE code pass, the hardware stores exported sign bits in an 8-bit FIFO and outputs them at a specified interval. This permits the CE code to calculate all of the pulse generator outputs at the beginning of its code pass and to rely on hardware to spread them over the MUX frame. The FIFO is reset at the beginning of each MUX frame. PLS_INTERVAL controls the delay to the first pulse update and the interval between subsequent updates. Its LSB is four CK_FIR cycles, or 4 * 203ns. If PLS_INTERVAL is zero, the FIFO is deactivated and the pulse outputs are updated immediately. Thus, the internal is 4*PLS_INTERVAL. For use with the standard CE code supplied by Teridian, PLS_INTERVAL is set to a fixed value of 81. PLS_INTERVAL is specified so that all of the pulse updates are output before the MUX frame completes. On-chip hardware provides a maximum pulse width feature: PLS_MAXWIDTH[7:0] selects a maximum negative pulse width to be `Nmax' updates per multiplexer cycle according to the formula: Nmax = (2*PLS_MAXWIDTH+1). If PLS_MAXWIDTH = 255, no width checking is performed. Given that PLS_INTERVAL = 81, the maximum pulse width is determined by: Maximum Pulse Width = (2 * PLS_MAXWIDTH +1) * 81*4*203ns = 65.9s + PLS_MAXWIDTH * 131.5s
Rev. 1.2
13
78M6612 Data Sheet
DS_6612_001
If the pulse period corresponding to the pulse rate exceeds the desired pulse width, a square wave with 50% duty-cycle is generated. The CE pulse output polarity is programmable to be either positive or negative. Pulse polarity may be inverted with PLS_INV. When this bit is set, the pulses are active high, rather than the more usual active low.
1.3.4 CE Functional Overview
The ADC processes one sample per channel per multiplexer cycle. Figure 4 shows the timing of the samples taken during one multiplexer cycle. The number of samples processed during one accumulation cycle is controlled by the I/O RAM registers PRE_SAMPS (0x2001[7:6]) and SUM_CYCLES (0x2001[5:0]). The integration time for each energy output is PRE_SAMPS * SUM_CYCLES / 2520.6, where 2520.6 is the sample rate [Hz] for demo firmware 6612_OMU_S2_URT_V1_07. For example, PRE_SAMPS = 42 and SUM_CYCLES = 50 will establish 2100 samples per accumulation cycle. PRE_SAMPS = 100 and SUM_CYCLES = 21 will result in the exact same accumulation cycle of 2100 samples or 833 ms. After an accumulation cycle is completed, the XFER_BUSY interrupt signals to the MPU that accumulated data are available.
1/32768Hz = 30.518s IB VB VA
IA
13/32768Hz = 397s per mux cycle
Figure 4: Samples from Multiplexer Cycle The end of each multiplexer cycle is signaled to the MPU by the CE_BUSY interrupt. At the end of each multiplexer cycle, status information, such as sag data and the digitized input signal, is available to the MPU.
833ms
20ms XFER_BUSY Interrupt to MPU
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Rev. 1.2
DS_6612_001 Figure 5: Accumulation Interval
78M6612 Data Sheet
Figure 5 shows the accumulation interval resulting from PRE_SAMPS = 42 and SUM_CYCLES = 50, consisting of 2100 samples of 397s each, followed by the XFER_BUSY interrupt. The sampling in this example is applied to a 50Hz signal.
Rev. 1.2
15
78M6612 Data Sheet
DS_6612_001
There is no correlation between the line signal frequency and the choice of PRE_SAMPS or SUM_CYCLES (even though when SUM_CYCLES = 42 one set of SUM_CYCLES happens to sample a period of 16.6 ms). Furthermore, sampling does not have to start when the line voltage crosses the zero line, and the length of the accumulation interval need not be an integer multiple of the signal cycles. It is important to note that the length of the accumulation interval, as determined by N ACC , the product of SUM_CYCLES and PRE_SAMPS, is not an exact multiple of 1000 ms. For example, if SUM_CYCLES = 60, and PRE_SAMPS = 00 (42), the resulting accumulation interval is:
=
N ACC 2520 60 42 = = = 999.75ms 32768Hz 2520.62 Hz fS 13
This means that accurate time measurements should be based on the RTC, not the accumulation interval.
1.4
80515 MPU Core
The 78M6612 includes an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle. Using a 5 MHz (4.9152 MHz) clock results in a processing throughput of 5 MIPS. The 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases. Normally a machine cycle is aligned with a memory fetch, therefore, most of the 1byte instructions are performed in a single cycle. This leads to an 8x performance (in average) improvement (in terms of MIPS) over the Intel 8051 device running at the same clock frequency. Actual processor clocking speed can be adjusted to the total processing demand of the application (measurement calculations, AMR management, memory management, LCD driver management and I/O management) using the I/O RAM register MPU_DIV[2:0]. Typical power and energy measurement functions based on the results provided by the internal 32-bit compute engine (CE) are available for the MPU as part of Teridian's standard library. A standard ANSI "C" 80515 application program library is available to help reduce design cycle.
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DS_6612_001
78M6612 Data Sheet
1.4.1 Memory Organization
The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces. Memory organization in the 80515 is similar to that of the industry standard 8051. There are three memory areas: Program memory (Flash), external data memory (XRAM), physically consisting of XRAM, CE DRAM, and I/O RAM, and internal data memory (Internal RAM). Table 3 shows the memory map. Table 3: Memory Map Address (hex) 0000-7FFF on 1K boundary 0000-07FF 1000-11FF 2000-20FF Memory Technology Flash Memory Flash Memory Static RAM Static RAM Static RAM Memory Type Typical Usage MPU Program and non-volatile data CE program MPU data XRAM, CE data Configuration RAM I/O RAM Wait States (at 5 MHz) 0 0 0 6 0 Memory Size (bytes) 32K 2K 2K 512 256
Non-volatile Non-volatile Volatile Volatile Volatile
Internal and External Data Memory: Both internal and external data memory are physically located on the 78M6612 IC. "External" data memory is defined as external to the 80515 MPU core. Program Memory: The 80515 can theoretically address up to 64 KB of program memory space from 0x0000 to 0xFFFF. Program memory is read when the MPU fetches instructions or performs a MOVC operation. After reset, the MPU starts program execution from location 0x0000. The lower part of the program memory includes reset and interrupt vectors. The interrupt vectors are spaced at 8-byte intervals, starting from 0x0003. External Data Memory: While the 80515 is capable of addressing up to 64 KB of external data memory (0x0000 to 0xFFFF), only the memory ranges shown in Table 3 are supported by the 78M6612. Contain Physical Memory: The 80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX @DPTR,A instruction. The MPU reads external data memory by executing a MOVX A,@Ri or MOVX A,@DPTR instruction (SFR USR2 provides the upper 8 bytes for the MOVX A,@Ri instruction). Clock Stretching: MOVX instructions can access fast or slow external RAM and external peripherals. The three low order bits of the CKCON register define the stretch memory cycles. Setting all the CKCON stretch bits to one allows access to very slow external RAM or external peripherals. Table 4 shows how the signals of the External Memory Interface change when stretch values are set from 0 to 7. The widths of the signals are counted in MPU clock cycles. The post-reset state of the CKCON register, which is in bold in the table, performs the MOVX instructions with a stretch value equal to 1.
Rev. 1.2
17
78M6612 Data Sheet Table 4: Stretch Memory Cycle Width CKCON Register CKCON[2] CKCON[1] CKCON[0] 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Stretch Value 0 1 2 3 4 5 6 7 Read Signals Width memaddr 1 2 3 4 5 6 7 8 memrd 1 2 3 4 5 6 7 8
DS_6612_001
Write Signal Width memaddr 2 3 4 5 6 7 8 9 memwr 1 1 2 3 4 5 6 7
There are two types of instructions, differing in whether they provide an eight-bit or sixteen-bit indirect address to the external data RAM. In the first type (MOVX A,@Ri), the contents of R0 or R1, in the current register bank, provide the eight lower-ordered bits of address. The eight high-ordered bits of address are specified with the USR2 SFR. This method allows the user paged access (256 pages of 256 bytes each) to all ranges of the external data RAM. In the second type of MOVX instruction (MOVX A,@DPTR), the data pointer generates a sixteen-bit address. This form is faster and more efficient when accessing very large data arrays (up to 64 Kbytes), since no additional instructions are needed to set up the eight high ordered bits of address. It is possible to mix the two MOVX types. This provides the user with four separate data pointers, two with direct access and two with paged access to the entire 64 KB of external memory range. Dual Data Pointer: The Dual Data Pointer accelerates the block moves of data. The standard Data Pointer (DPTR) is a 16-bit register (DPH, DPL) that is used to address external memory or peripherals. In the 80515 core, the standard data pointer is called DPTR, the second data pointer is called DPTR1 (DPH1, DPL1). The data pointer select bit chooses the active pointer. The data pointer select bit is located at the LSB of the DPS register (DPS[0]). DPTR is selected when DPS[0] = 0 and DPTR1 is selected when DPS[0] = 1. The user switches between pointers by toggling the LSB of the DPS register. All data pointer-related instructions use the currently selected data pointer for any activity. The second data pointer may not be supported by certain compilers. Internal Data Memory: The Internal data memory provides 256 bytes (0x00 to 0xFF) of data memory. The internal data memory address is always 1 byte wide and can be accessed by either direct or indirect addressing. The Special Function Registers occupy the upper 128 bytes. This SFR area is available only by direct addressing. Indirect addressing accesses the upper 128 bytes of Internal RAM. Internal Data Memory: The lower 128 bytes contain working registers and bit-addressable memory. The lower 32 bytes form four banks of eight registers (R0-R7). Two bits on the program memory status word (PSW) select which bank is in use. The next 16 bytes form a block of bit-addressable memory space at bit addresses 0x00-0x7F. All of the bytes in the lower 128 bytes are accessible through direct or indirect addressing. Table 5 shows the internal data memory map.
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DS_6612_001 Table 5: Internal Data Memory Map Address 0xFF 0x80 0x7F 0x30 0x2F 0x20 0x1F 0x00 Direct Addressing Special Function Registers (SFRs) Byte-addressable area Bit-addressable area Register banks R0...R7 Indirect Addressing RAM
78M6612 Data Sheet
1.4.2 Special Function Registers (SFRs)
A map of the Special Function Registers is shown in Table 6. Table 6: Special Function Registers Locations BitAddressable X000 F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 IEN0 P2 S0CON P1 TCON P0 IP0 DIR2 S0BUF DIR1 TMOD SP INTBITS B WDI A WDCON PSW T2CON IRCON IEN1 IP1 S0RELH FLSHCTL S0RELL DIR0 IEN2 DPS TL0 DPL TL1 DPH S1CON S1BUF ERASE TH0 DPL1 TH1 DPH1 CKCON WDTREL PCON S1RELL EEDATA EECTRL S1RELH USR2 FPAG X001 X010 Byte-Addressable X011 X100 X101 X110 X111 FF F7 EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 8F 87
Hex\Bin
Hex/Bin
Only a few addresses are occupied, the others are not implemented. SFRs specific to the 78M6612 are shown in bold print. Any read access to unimplemented addresses will return undefined data, while any write access will have no effect. The registers at 0x80, 0x88, 0x90, etc., are bit-addressable, all others are byte-addressable.
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19
78M6612 Data Sheet
DS_6612_001
1.4.3 Special Function Registers (Generic 80515 SFRs)
Table 7 shows the location of the SFRs and the value they assume at reset or power-up.
Table 7: Special Function Registers Reset Values Name P0 SP DPL DPH DPL1 DPH1 WDTREL PCON TCON TMOD TL0 TL1 TH0 TH1 CKCON P1 DPS S0CON S0BUF IEN2 S1CON S1BUF S1RELL P2 IEN0 IP0 S0RELL IEN1 IP1 S0RELH S1RELH USR2 IRCON T2CON PSW WDCON A B 20 Location 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x90 0x92 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0xA0 0xA8 0xA9 0xAA 0xB8 0xB9 0xBA 0xBB 0xBF 0xC0 0xC8 0xD0 0xD8 0xE0 0xF0 Reset Value Description 0xFF 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xD9 0x00 0x00 0x03 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Port 0 (DIO0) Stack Pointer Data Pointer 0 Low (Standard Data Pointer) Data Pointer 0 High (Standard Data Pointer) Data Pointer 1 Low (Second Data Pointer) Data Pointer 1 High (Second Data Pointer) Watchdog Timer Reload register UART Speed Control Timer/Counter Control Timer Mode Control Timer 0, low byte Timer 1, high byte Timer 0, low byte Timer 1, high byte Clock Control (Stretch=1) Port 1 (DIO1) Data Pointer select Register Serial Port 0, Control Register Serial Port 0, Data Buffer Interrupt Enable Register 2 Serial Port 1, Control Register Serial Port 1, Data Buffer Serial Port 1, Reload Register, low byte Port 2 (DIO2) Interrupt Enable Register 0 Interrupt Priority Register 0 Serial Port 0, Reload Register, low byte Interrupt Enable Register 1 Interrupt Priority Register 1 Serial Port 0, Reload Register, high byte Serial Port 1, Reload Register, high byte User 2 Port, high address byte for MOVX@Ri Interrupt Request Control Register Polarity for INT2 and INT3 Program Status Word Baud Rate Control Register (only WDCON.7 bit used) Accumulator B Register
Page
21 20 20 20 17 17 30 28 26 27 27 27 27 27 16 21 17 24 23 32 25 23 23 21 31 29 23 31 36 23 23 16 33 32 20 23 20 20 Rev. 1.2
DS_6612_001
78M6612 Data Sheet
Accumulator (ACC, A): ACC is the accumulator register. Most instructions use the accumulator to hold the operand. The mnemonics for accumulator-specific instructions refer to accumulator as "A", not ACC. B Register: The B register is used during multiply and divide instructions. It can also be used as a scratch-pad register to hold temporary data. Program Status Word (PSW) Table 8: PSW Register MSB CV Bit PSW[7] PSW[6] PSW[5] AC F0 Function Carry flag. Auxiliary Carry flag for BCD operations. General purpose Flag 0 available for user. F0 is not to be confused with the F0 flag in the CE STATUS register. PSW[4] RS1 Register bank select control bits. The contents of RS1 and RS0 select the working register bank: RS1/RS0 PSW[3] RS0 00 01 10 11 PSW[2] PSW[1] PSW[0] OV - P Overflow flag. User defined flag. Parity flag, affected by hardware to indicate odd / even number of "one" bits in the Accumulator, i.e. even parity. Bank Selected Bank 0 Bank 1 Bank 2 Bank 3 Location (0x00 - 0x07) (0x08 - 0x0F) (0x10 - 0x17) (0x18 - 0x1F) RS1 RS OV - P LSB
Symbol CV AC F0
Stack Pointer (SP): The stack pointer is a 1-byte register initialized to 0x07 after reset. This register is incremented before PUSH and CALL instructions, causing the stack to begin at location 0x08. Data Pointer: The data pointer (DPTR) is 2 bytes wide. The lower part is DPL, and the highest is DPH. It can be loaded as two registers (e.g. MOV DPL,#data8). It is generally used to access external code or data space (e.g. MOVC A,@A+DPTR or MOVX A,@DPTR respectively). Program Counter: The program counter (PC) is 2 bytes wide and initialized to 0x0000 after reset. This register is incremented when fetching operation code or when operating on data from program memory.
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21
78M6612 Data Sheet
DS_6612_001
Port Registers: The I/O ports are controlled by Special Function Registers P0, P1, and P2. The contents of the SFR can be observed on corresponding pins on the chip. Writing a `1' to any of the ports (see Table 9) causes the corresponding pin to be at high level (V3P3), and writing a `0' causes the corresponding pin to be held at low level (GND). The data direction registers DIR0, DIR1, and DIR2 define individual pins as input or output pins (see the Section 1.5.7 Digital I/O for details). Table 9: Port Registers Register P0 DIR0 P1 DIR1 P2 DIR2 SFR Address 0x80 0xA2 0x90 0x91 0xA0 0xA1 R/W R/W R/W R/W R/W R/W R/W Description Register for port 0 read and write operations (pins DIO4...DIO7). Data direction register for port 0. Setting a bit to 1 means that the corresponding pin is an output. Register for port 1 read and write operations (pins DIO8...DIO11, DIO14-DIO15). Data direction register for port 1. Register for port 2 read and write operations (pins DIO16...DIO17, DIO19...DIO21). Data direction register for port 2.
All DIO ports on the chip are bi-directional. Each consists of a Latch (SFR P0 to P2), an output driver, and an input buffer, therefore the MPU can output or read data through any of these ports. Even if a DIO pin is configured as an output, the state of the pin can still be read by the MPU, for example when counting pulses issued via DIO pins that are under CE control. The technique of reading the status of or generating interrupts based on DIO pins configured as outputs, can be used to implement pulse counting.
1.4.4 Special Function Registers Specific to the 78M6612
Table 10 shows the location and description of the 78M6612-specific SFRs. Table 10: Special Function Registers Register ERASE Alternative Name FLSH_ERASE SFR Address 0x94 R/W W Description This register is used to initiate either the Flash Mass Erase cycle or the Flash Page Erase cycle. Specific patterns are expected for FLSH_ERASE in order to initiate the appropriate Erase cycle (default = 0x00). 0x55 - Initiate Flash Page Erase cycle. Must be preceded by a write to FLSH_PGADR @ SFR 0xB7. 0xAA - Initiate Flash Mass Erase cycle. Must be preceded by a write to FLSH_MEEN @ SFR 0xB2 and the debug port must be enabled. Any other pattern written to FLSH_ERASE will have no effect. Flash Page Erase Address register containing the Flash memory page address (page 0 through 127) that will be erased during the Page Erase cycle (default = 0x00). Rev. 1.2
FPAG
FLSH_PGADR
0xB7
R/W
22
DS_6612_001 Register Alternative Name SFR Address 0x9E 0x9F R/W Description
78M6612 Data Sheet
Must be re-written for each new Page Erase cycle. EEDATA EECTRL R/W R/W I2C EEPROM interface data register. I2C EEPROM interface control register. If the MPU wishes to write a byte of data to EEPROM, it places the data in EEDATA and then writes the `Transmit' code to EECTRL. The write to EECTRL initiates the transmit sequence. See Section 1.5.10 EEPROM Interface for a description of the command and status bits available for EECTRL. Bit 0 (FLSH_PWE): Program Write Enable: 0 - MOVX commands refer to XRAM Space, normal operation (default). 1 - MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR. This bit is automatically reset after each byte written to Flash. Writes to this bit are inhibited when interrupts are enabled. Bit 1 (FLSH_MEEN): Mass Erase Enable: 0 - Mass Erase disabled (default). 1 - Mass Erase enabled. Must be re-written for each new Mass Erase cycle. Bit 6 (SECURE): Enables security provisions that prevent external reading of Flash memory and CE program RAM. This bit is reset on chip reset and may only be set. Attempts to write zero are ignored. Bit 7 (PREBOOT): Indicates that the preboot sequence is active. Only byte operations on the whole WDI register should be used when writing. The byte must have all bits set except the bits that are to be cleared. The multi-purpose register WDI contains the following bits: Bit 0 (IE_XFER): XFER Interrupt Flag: This flag monitors the XFER_BUSY interrupt. It is set by hardware and must be cleared by the interrupt handler. Bit 1 (IE_RTC): RTC Interrupt Flag: This flag monitors the RTC_1SEC interrupt. It is set by hardware and must be cleared by the interrupt handler. Bit 7 (WD_RST): WD Timer Reset: Read: Reads the PLL_FALL interrupt flag. Write 0: Clears the PLL_FALL interrupt flag. Write 1: Resets the watch dog timer . Interrupt inputs. The MPU may read these bits to see the input to external interrupts INT0, INT1, up to INT6. These bits do not have any memory and are primarily intended for debug use. 23
FLSHCRL
0xB2
R/W
W
R/W
R
WDI
0xE8 R/W
R/W
W
INTBITS
INT0...INT6
0xF8
R
Rev. 1.2
78M6612 Data Sheet
DS_6612_001
1.4.5 Instruction Set
All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set and of the associated op-codes is contained in the Teridian 78M6612 Firmware Developer's Manual.
1.4.6 UARTs
The 78M6612 includes a UART (UART0) that can be programmed to communicate with a variety of external devices. A second UART (UART1) is connected to the optical port, as described in Section 1.5.6 Optical Interface. The UARTs are dedicated 2-wire serial interfaces, which can communicate with an external device at up to 38,400 bits/s. The operation of each pin is as follows: UART RX: Serial input data are applied at this pin. Conforming to RS-232 standard, the bytes are input LSB first. * UART TX: This pin is used to output the serial data. The bytes are output LSB first. The 78M6612 has several UART-related registers for the control and buffering of serial data.
The serial buffers consist of sets of two separate registers (one set for each UART), a transmit buffer (S0BUF, S1BUF) and a receive buffer (R0BUF, R1BUF). Writing data to the transmit buffer starts the transmission by the associated UART. Received data are available by reading from the receive buffer. Both UARTs can simultaneously transmit and receive data. WDCON[7] selects whether timer 1 or the internal baud rate generator is used. All UART transfers are pro-
*
grammable for parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for variable communication baud rates from 300 to 38,400 bps. Table 11 shows how the baud rates are calculated. Table 12 shows the selectable UART operation modes. Table 11: Baud Rate Generation Using Timer 1 (WDCON[7] = 0) UART 0 UART 1 2SMOD * f CKMPU / (384 * (256-TH1)) N/A Using Internal Baud Rate Generator (WDCON[7] = 1) 2SMOD * f CKMPU /(64 * (210-S0REL)) f CKMPU /(32 * (210-S1REL))
S0REL and S1REL are 10-bit values derived by combining bits from the respective timer reload registers. SMOD is the SMOD bit in the SFR PCON. TH1 is the high byte of timer 1. Table 12: UART Modes
UART 0 Mode 0 UART 1
N/A Start bit, 8 data bits, stop bit, variable baud rate (internal baud rate generator or timer 1). Start bit, 8 data bits, parity, stop bit, fixed baud rate 1/32 or 1/64 of f CKMPU. Start bit, 8 data bits, parity, stop bit, variable baud rate (internal baud rate generator or timer 1).
Start bit, 8 data bits, parity, stop bit, variable baud rate (internal baud rate generator). Start bit, 8 data bits, stop bit, variable baud rate (internal baud rate generator). N/A
Mode 1
Mode 2
Mode 3
N/A
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DS_6612_001
78M6612 Data Sheet
Parity of serial data is available through the P flag of the accumulator. Seven-bit serial modes with parity, such as those used by the FLAG protocol, can be simulated by setting and reading bit 7 of 8-bit output data. Seven-bit serial modes without parity can be simulated by setting bit 7 to a constant 1. 8-bit serial modes with parity can be simulated by setting and reading the 9th bit, using the control bits TB80 (S0CON[3]) and TB81 (S1CON[3]) in the S0CON and S1CON SFRs for transmit and RB81 (S1CON[2]) for receive operations. SM20 (S0CON[5]) and SM21 (S1CON[5]) can be used as handshake signals for inter-processor communication in multi-processor systems. Serial Interface 0 Control Register (S0CON) The function of the UART0 depends on the setting of the Serial Port Control Register S0CON. Table 13: The S0CON Register MSB SM0 Bit S0CON[7] SM1 SM20 Function These two bits set the UART0 mode: Mode 0 S0CON[6] SM1 1 2 3 S0CON[5] S0CON[4] S0CON[3] SM20 REN0 TB80 Description N/A 8-bit UART 9-bit UART 9-bit UART SM0 0 0 1 1 SM1 0 1 0 1 REN0 TB80 RB80 TI0 LSB RI0
Symbol SM0
Enables the inter-processor communication feature. If set, enables serial reception. Cleared by software to disable reception. The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the MPU, depending on the function it performs (parity check, multiprocessor communication etc.). In modes 2 and 3, it is the 9th data bit received. In Mode 1, if SM20 is 0, RB80 is the stop bit. In mode 0 this bit is not used. Must be cleared by software. Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be cleared by software. Receive interrupt flag, set by hardware after completion of a serial reception. Must be cleared by software.
S0CON[2]
RB80
S0CON[1] S0CON[0]
TI0 RI0
Rev. 1.2
25
78M6612 Data Sheet Serial Interface 1 Control Register (S1CON)
DS_6612_001
The function of the serial port depends on the setting of the Serial Port Control Register S1CON. Table 14: The S1CON Register MSB SM Bit S1CON[7] Symbol SM - SM21 Function Sets the baud rate for UART1 SM 0 1 S1CON[5] S1CON[4] S1CON[3] SM21 REN1 TB81 Mode A B Description 9-bit UART 8-bit UART Baud Rate variable variable REN1 TB81 RB81 TI1 LSB RI1
Enables the inter-processor communication feature. If set, enables serial reception. Cleared by software to disable reception. The 9th transmitted data bit in Mode A. Set or cleared by the MPU, depending on the function it performs (parity check, multiprocessor communication etc.). In Modes A and B, it is the 9th data bit received. In Mode B, if SM21 is 0, RB81 is the stop bit. Must be cleared by software. Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be cleared by software. Receive interrupt flag, set by hardware after completion of a serial reception. Must be cleared by software.
S1CON[2] S1CON[1] S1CON[0]
RB81 TI1 RI1
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78M6612 Data Sheet
1.4.7 Timers and Counters
The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured for counter or timer operations. In timer mode, the register is incremented every machine cycle, meaning that it counts up after every 12 periods of the MPU clock signal. In counter mode, the register is incremented when the falling edge is observed at the corresponding input signal T0 or T1 (T0 and T1 are the timer gating inputs derived from certain DIO pins, see the DIO Ports section). Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the oscillator frequency. There are no restrictions on the duty cycle, however to ensure proper recognition of 0 or 1 state, an input should be stable for at least 1 machine cycle. The timers/counters are controlled by the TCON Register Timer/Counter Control Register (TCON) Table 15: The TCON Register MSB TF1 Bit TCON[7] TCON[6] TCON[5] TCON[4] TCON[3] TCON[2] TCON[1] TCON[0] TR1 TF0 Function The Timer 1 overflow flag is set by hardware when Timer 1 overflows. This flag can be cleared by software and is automatically cleared when an interrupt is processed. Timer 1 Run control bit. If cleared, Timer 1 stops. Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag can be cleared by software and is automatically cleared when an interrupt is processed. Timer 0 Run control bit. If cleared, Timer 0 stops. Interrupt 1 edge flag is set by hardware when the falling edge on external pin int1 is observed. Cleared when an interrupt is processed. Interrupt 1 type control bit. Selects either the falling edge or low level on input pin to cause an interrupt. Interrupt 0 edge flag is set by hardware when the falling edge on external pin int0 is observed. Cleared when an interrupt is processed. Interrupt 0 type control bit. Selects either the falling edge or low level on input pin to cause interrupt. TR0 IE1 IT1 IE0 LSB IT0
Symbol TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function Registers (TMOD and TCON) are used to select the appropriate mode.
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78M6612 Data Sheet Timer/Counter Mode Control Register (TMOD)
DS_6612_001
Bits TR1 (TCON[6]) and TR0 (TCON[4]) in the TCON register (see Table 15) start their associated timers when set. Table 16: The TMOD Register MSB GATE C/T M1 M0 GATE C/T M1 LSB M0
Timer 1 Bit TMOD[7] TMOD[3] TMOD[6] TMOD[2] TMOD[5] TMOD[1] TMOD[4] TMOD[0] Symbol Gate Function
Timer 0
If set, enables external gate control (pin int0 or int1 for Counter 0 or 1, respectively). When int0 or int1 is high, and TRX bit is set (see TCON register), a counter is incremented every falling edge on t0 or t1 input pin Selects Timer or Counter operation. When set to 1, a Counter operation is performed. When cleared to 0, the corresponding register will function as a Timer. Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in TMOD description. Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in TMOD description. Table 17: Timers/Counters Mode Description
C/T
M1 M0
M1 0
M0 0
Mode Mode 0
Function 13-bit Counter/Timer with 5 lower bits in the TL0 or TL1 register and the remaining 8 bits in the TH0 or TH1 register (for Timer 0 and Timer 1, respectively). The 3 high order bits of TL0 and TL1 are held at zero. 16-bit Counter/Timer. 8-bit auto-reload Counter/Timer. The reload value is kept in TH0 or TH1, while TL0 or TL1 is incremented every machine cycle. When TL(x) overflows, a value from TH(x) is copied to TL(x). If Timer 1 M1 and M0 bits are set to 1, Timer 1 stops. If Timer 0 M1 and M0 bits are set to 1, Timer 0 acts as two independent 8-bit Timer/Counters.
0 1
1 0
Mode 1 Mode 2
1
1
Mode 3
Note: In Mode 3, TL0 is affected by TR0 and gate control bits, and sets the TF0 flag on overflow, while TH0 is affected by the TR1 bit, and the TF1 flag is set on overflow. Table 18 specifies the combinations of operation modes allowed for timer 0 and timer 1. Table 18: Timer Modes Timer 1 Mode 0 Timer 0 - mode 0 Timer 0 - mode 1 Timer 0 - mode 2 28 YES YES Not allowed Mode 1 YES YES Not allowed Mode 2 YES YES YES Rev. 1.2
DS_6612_001 Timer/Counter Mode Control Register (PCON) The SMOD bit in the PCON register doubles the baud rate when set. Table 19: The PCON Register MSB SMOD Bit PCON[7] 1.4.8 Symbol SMOD - - Function Baud rate control. - - - -
78M6612 Data Sheet
LSB -
WD Timer (Software Watchdog Timer)
The software watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles. After a reset, the watchdog timer is disabled and all registers are set to zero. The watchdog consists of a 16-bit counter (WDT), a reload register (WDTREL), prescalers (by 2 and by 16), and control logic. Once the watchdog is started, it cannot be stopped unless the internal reset signal becomes active. Note: It is recommended to use the hardware watchdog timer instead of the software watchdog timer.
WD Timer Start Procedure: The WDT is started by setting the SWDT flag. When the WDT register enters the state 0x7CFF, an asynchronous WDTS signal will become active. The signal WDTS sets bit 6 in the IP0 register and requests a reset state. WDTS is cleared either by the reset signal or by changing the state of the WDT timer. Refreshing the WD Timer: The watchdog timer must be refreshed regularly to prevent the reset request signal from becoming active. This requirement imposes an obligation on the programmer to issue two instructions. The first instruction sets WDT and the second instruction sets SWDT. The maximum delay allowed between setting WDT and SWDT is 12 clock cycles. If this period has expired and SWDT has not been set, the WDT is automatically reset, otherwise the watchdog timer is reloaded with the content of the WDTREL register and the WDT is automatically reset. Since the WDT requires exact timing, firmware needs to be designed with special care in order to avoid unwanted WDT resets. Teridian strongly discourages the use of the software WDT.
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78M6612 Data Sheet Special Function Registers for the WD Timer Interrupt Enable 0 Register (IEN0) Table 20: The IEN0 Register MSB EAL Bit IEN0[6] WDT ET2 ES0 ET1 EX1 ET0 LSB EX0
DS_6612_001
Symbol WDT
Function Watchdog timer refresh flag. Set to initiate a refresh of the watchdog timer. Must be set directly before SWDT is set to prevent an unintentional refresh of the watchdog timer. WDT is reset by hardware 12 clock cycles after it has been set.
Note: The remaining bits in the IEN0 register are not used for watchdog control.
Interrupt Enable 1 Register (IEN1) Table 21: The IEN1 Register MSB EXEN2 Bit IEN1[6] SWDT EX6 EX5 EX4 EX3 EX2 LSB -
Symbol SWDT
Function Watchdog timer start/refresh flag. Set to activate/refresh the watchdog timer. When directly set after setting WDT, a watchdog timer refresh is performed. Bit SWDT is reset by the hardware 12 clock cycles after it has been set.
Note: The remaining bits in the IEN1 register are not used for watchdog control.
Interrupt Priority 0 Register (IP0) Table 22: The IP0 Register MSB - Bit IP0[6] WDTS IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 LSB IP0.0
Symbol WDTS
Function Watchdog timer status flag. Set when the watchdog timer was started. Can be read by software.
Note: The remaining bits in the IP0 register are not used for watchdog control.
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DS_6612_001 Watchdog Timer Reload Register (WDTREL) Table 23: The WDTREL Register MSB 7 Bit WDTREL[7] WDTREL[6] to WDTREL[0] Symbol 7 6 5 Function 4 3 2 1
78M6612 Data Sheet
LSB 0
Prescaler select bit. When set, the watchdog is clocked through an additional divide-by-16 prescaler. Seven bit reload value for the high-byte of the watchdog timer. This value is loaded to the WDT when a refresh is triggered by a consecutive setting of bits WDT and SWDT.
6-0
The WDTREL register can be loaded and read at any time. 1.4.9 Interrupts
The 80515 provides 11 interrupt sources with four priority levels. Each source has its own request flag(s) located in a special function register (TCON, IRCON, and SCON). Each interrupt requested by the corresponding flag can be individually enabled or disabled by the enable bits in SFRs IEN0, IEN1, and IEN2. External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of the 78M6612, for example the CE, DIO, RTC EEPROM interface.
1.4.9.1 Interrupt Overview When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 37. Once interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a return from the RETI instruction. When a RETI is performed, the MPU will return to the instruction that would have been next when the interrupt occurred. When the interrupt condition occurs, the MPU will also indicate this by setting a flag bit. This bit is set regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per machine cycle, then samples are polled by the hardware. If the sample indicates a pending interrupt when the interrupt is enabled, then the interrupt request flag is set. On the next instruction cycle, the interrupt will be acknowledged by hardware forcing an LCALL to the appropriate vector address, if the following conditions are met: * * * No interrupt of equal or higher priority is already in progress. An instruction is currently being executed and is not completed. The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or IP1.
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78M6612 Data Sheet Special Function Registers for Interrupts The following SFR registers control the interrupt functions:
DS_6612_001
* The interrupt enable Registers: IEN0, IEN1 and IEN2 (see Table 24, Table 25 and Table 26). * The Timer/Counter control registers: The Timer/Counter control registers: TCON and T2CON (see Table 27 and Table 28). * The interrupt request register: IRCON (see Table 29). * The interrupt priority registers: IP0 and IP1 (see Table 33 and Table 34). Interrupt Enable 0 Register (IEN0) Table 24: The IEN0 Register MSB EAL Bit IEN0[7] IEN0[6] IEN0[5] IEN0[4] IEN0[3] IEN0[2] IEN0[1] IEN0[0] WDT Symbol EAL WDT - ES0 ET1 EX1 ET0 EX0 ES0=0 - disable serial channel 0 interrupt. ET1=0 - disable timer 1 overflow interrupt. EX1=0 - disable external interrupt 1. ET0=0 - disable timer 0 overflow interrupt. EX0=0 - disable external interrupt 0. - ES0 Function EAL=0 - disable all interrupts. Not used for interrupt control. ET1 EX1 ET0 LSB EX0
Interrupt Enable 1 Register (IEN1) Table 25: The IEN1 Register MSB - SWDT Bit IEN1[7] IEN1[6] IEN1[5] IEN1[4] IEN1[3] IEN1[2] IEN1[1] IEN1[0] EX6 Symbol - SWDT EX6 EX5 EX4 EX3 EX2 - Not used for interrupt control. EX6=0 - disable external interrupt 6. EX5=0 - disable external interrupt 5. EX4=0 - disable external interrupt 4. EX3=0 - disable external interrupt 3. EX2=0 - disable external interrupt 2. EX5 Function EX4 EX3 EX2 LSB -
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DS_6612_001 Interrupt Enable 2 Register (IEN2) Table 26: The IEN2 Register MSB - Bit IEN2[0] Symbol ES1 - Function ES1=0 - disable serial channel 1 interrupt. - - - - -
78M6612 Data Sheet
LSB ES1
Timer/Counter Control Register (TCON) Table 27: The TCON Register MSB TF1 Bit TCON[7] TCON[6] TCON[5] TCON[4] TCON[3] TCON[2] TCON[1] TCON[0] Symbol TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 TR1 Function Timer 1 overflow flag. Not used for interrupt control. Timer 0 overflow flag. Not used for interrupt control. External interrupt 1 flag. External interrupt 1 type control bit. External interrupt 0 flag. External interrupt 0 type control bit. TF0 TR0 IE1 IT1 IE0 LSB IT0
Timer2/Counter2 Control Register (T2CON) Table 28: The T2CON Bit Functions Bit T2CON[7] T2CON[6] T2CON[5] TCON[4] ... T2CON[0] Symbol - I3FR I2FR - Function Not used. Polarity control for INT3: 0 - falling edge, 1 - rising edge. Polarity control for INT3: 0 - falling edge, 1 - rising edge. Not used.
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78M6612 Data Sheet Interrupt Request Register (IRCON) Table 29: The IRCON Register MSB - Bit IRCON[7] IRCON[6] IRCON[5] IRCON[4] IRCON[3] IRCON[2] IRCON[1] IRCON[0] Symbol - - IEX6 IEX5 IEX4 IEX3 IEX2 - External interrupt 6 edge flag. External interrupt 5 edge flag. External interrupt 4 edge flag. External interrupt 3 edge flag. External interrupt 2 edge flag. - Function EX6 IEX5 IEX4 IEX3 IEX2
DS_6612_001
LSB -
Only TF0 and TF1 (timer 0 and timer 1 overflow flag) will be automatically cleared by hardware when the service routine is called (Signals T0ACK and T1ACK - port ISR - active high when the service routine is called).
1.4.9.2 External Interrupts The 78M6612 MPU allows seven external interrupts. These are connected as shown in Table 30. The direction of interrupts 2 and 3 is programmable in the MPU. Interrupts 2 and 3 should be programmed for falling sensitivity. The generic 8051 MPU literature states that interrupt 4 through 6 are defined as rising edge sensitive. Thus, the hardware signals attached to interrupts 5 and 6 are inverted to achieve the edge polarity shown in Table 30. Table 30: External MPU Interrupts External Interrupt 0 1 2 3 4 5 6 Connection Digital I/O High Priority Digital I/O Low Priority FWCOL0, FWCOL1 CE_BUSY PLL_OK (rising), PLL_OK (falling) EEPROM busy XFER_BUSY OR RTC_1SEC Polarity see DIO_Rx see DIO_Rx falling falling rising falling falling Flag Reset automatic automatic automatic automatic automatic automatic manual
FWCOLx interrupts occur when the CE collides with a Flash write attempt. See the Flash write description in Section 1.5.5 for more detail. SFR (special function register) enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own flag bit, which is set by the interrupt hardware, and reset by the MPU interrupt handler. Note that XFER_BUSY, RTC_1SEC, FWCOL0, FWCOL1, PLLRISE, PLLFALL, have their own enable and flag bits in addition to the interrupt 6, 4, and 2 enable and flag bits. 34 Rev. 1.2
DS_6612_001
78M6612 Data Sheet
IE0 through IEX6 are cleared automatically when the hardware vectors to the interrupt handler. The other flags, IE_XFER through IE_WAKE, are cleared by writing a zero to them. Since these bits are in a bit-addressable SFR byte, common practice would be to clear them with a bit operation. This is to be avoided. The hardware implements bit operations as a byte wide read-modify-write hardware macro. If an interrupt occurs after the read, but before the write, its flag will be cleared unintentionally. The proper way to clear the flag bits is to write a byte mask consisting of all ones except for a zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore ones written to them. Table 31: Interrupt Enable and Flag Bits Interrupt Enable Name EX0 EX1 EX2 EX3 EX4 EX5 EX6 EX_XFER EX_RTC EX_FWCOL EX_PLL Location SFR A8[[0] SFR A8[2] SFR B8[1] SFR B8[2] SFR B8[3] SFR B8[4] SFR B8[5] 2002[0] 2002[1] 2007[4] 2007[5] Interrupt Flag Name IE0 IE1 IEX2 IEX3 IEX4 IEX5 IEX6 IE_XFER IE_RTC IE_FWCOL0 IE_FWCOL1 IE_PLLRISE IE_PLLFALL IE_WAKE Location SFR 88[1] SFR 88[3] SFR C0[1] SFR C0[2] SFR C0[3] SFR C0[4] SFR C0[5] SFR E8[0] SFR E8[1] SFR E8[3] SFR E8[2] SFRE8[6] SFRE8[7] SFRE8[5] Interrupt Description External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 XFER_BUSY interrupt (int 6) RTC_1SEC interrupt (int 6) FWCOL0 interrupt (int 2) FWCOL1 interrupt (int 2) PLL_OK rise interrupt (int 4) PLL_OK fall interrupt (int 4) AUTOWAKE flag
The AUTOWAKE flag bit is shown in Table 31 because it behaves similarly to interrupt flags, even though it is not actually related to an interrupt. This bit is set by hardware when the MPU wakes from a rising edge on wake timer timeout. The bit is reset by writing a zero. Each interrupt has its own flag bit, which is set by the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5). XFER_BUSY and RTC_1SEC, which are OR-ed together, have their own enable and flag bits in addition to the interrupt 6 enable and flag bits (see Table 31), and these interrupts must be cleared by the MPU software. When servicing the XFER_BUSY and RTC_1SEC interrupts, special care must be taken to avoid lock-up conditions: If, for example, the XFER_BUSY interrupt is serviced, control must not return to the main program without checking the RTC_1SEC flag. If this rule is ignored, a RTC_1SEC interrupt appearing during the XFER_BUSY service routine will disable the processing of any XFER_BUSY or RTC_1SEC interrupt, since both interrupts are edge-triggered. The external interrupts are connected as shown in Table 31. The polarity of interrupts 2 and 3 is programmable in the MPU via the I3FR and I2FR bits in T2CON. Interrupts 2 and 3 should be programmed for falling sensitivity. The generic 8051 MPU literature states that interrupts 4 through 6 are defined as rising edge sensitive. Thus, the hardware signals attached to interrupts 5 and 6 are inverted to achieve the edge polarity shown in Table 31.
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78M6612 Data Sheet
DS_6612_001
SFR (special function register) enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own flag bit that is set by the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5). XFER_BUSY and RTC_1SEC, which are OR-ed together, have their own enable and flag bits in addition to the interrupt 6 enable and flag bits, and these interrupts must be cleared by the MPU software. 1.4.9.3 Interrupt Priority Level Structure All interrupt sources are combined in groups, as shown in Table 32. Table 32: Priority Level Groups Group 0 1 2 3 4 5 External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial channel 0 interrupt - Serial channel 1 interrupt - - - - - External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6
Each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit in the special function register IP0 and one in IP1. If requests of the same priority level are received simultaneously, an internal polling sequence as per Table 36 determines which request is serviced first. Figure 6 gives an overview of the interrupt structure. IEN enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own flag bit that is set by the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5). XFER_BUSY and RTC_1SEC, which are OR-ed together, have their own enable and flag bits in addition to the interrupt 6 enable and flag bits and these interrupts must be cleared by the MPU software.
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DS_6612_001 Interrupt Priority 0 Register (IP0) Table 33: The IP0 Register MSB - WDTS IP0[5] IP0[4] IP0[3] IP0[2] IP0[1]
78M6612 Data Sheet
LSB IP0[0]
Note: WDTS is not used for interrupt controls. Interrupt Priority 1 Register (IP1) Table 34: The IP1 Register MSB - - IP1[5] IP1[4] IP1[3] IP1[2] IP1[1] LSB IP1[0]
Table 35: Priority Levels IP1[x] 0 0 1 1 IP0[x] 0 1 0 1 Priority Level Level0 (lowest) Level1 Level2 Level3 (highest)
Table 36: Interrupt Polling Sequence External interrupt 0 Serial channel 1 interrupt Timer 0 interrupt External interrupt 2 External interrupt 1 External interrupt 3 Timer 1 interrupt External interrupt 4 Serial channel 0 interrupt External interrupt 5 External interrupt 6 Polling sequence
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78M6612 Data Sheet 1.4.9.4 Interrupt Sources and Vectors Table 37 shows the interrupts with their associated flags and vector addresses. Table 37: Interrupt Vectors Interrupt Request Flag Description IE0 TF0 IE1 TF1 RI0/TI0 RI1/TI1 IEX2 IEX3 IEX4 IEX5 IEX6 External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial channel 0 interrupt Serial channel 1 interrupt External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6
DS_6612_001
Interrupt Vector Address 0x0003 0x000B 0x0013 0x001B 0x0023 0x0083 0x004B 0x0053 0x005B 0x0063 0x006B
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Internal/ External Source Individual Interrupt Flags General Interrupt Flags Logic and Polarity Selection Interrupt Control Register Interrupt Enable
78M6612 Data Sheet
Priority Assignment
IEN0[7]
IEN0[0]
DIO
IE0 IP1[0]/ IP0[0]
Polling Sequence
RI1 UART1 (optical) TI1 >=1
IEN2[0]
IEN0[1] Timer 0 TF0 IEN1[1]
Flash Write Collision
IE_FWCOL0 IE_FWCOL1
IP1[1]/ IP0[1]
Interrupt Vector
INT2
I2F R
IRCON[1] IEN0[2]
DIO
IE1 IEN1[2] IP1[2]/ IP0[2]
CE_BUSY
INT3
I3F R
IRCON[2]
IEN0[3] Timer 1 TF1 IEN1[3] PLL OK
IE_PLLRISE IE_PLLFALL
IP1[3]/ IP0[3]
INT4
IRCON[3]
RI0 UART0 TI0 >=1
IEN0[4] IP1[4]/ IP0[4]
IEN1[4] EEPROM/ I2C INT5 IRCON[4] IEN1[5]
XFER_BUSY
IE_XFER
IRCON[5] INT6
IP1[5]/ IP0[5]
RTC_1S
IE_RTC
Figure 6: Interrupt Structure
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78M6612 Data Sheet
DS_6612_001
1.5
On-Chip Resources
1.5.1 Oscillator
The 78M6612 oscillator drives a standard 32.768 kHz watch crystal. These crystals are accurate and do not require a high-current oscillator circuit. The 78M6612 oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability.
1.5.2 PLL and Internal Clocks
Timing for the device is derived from the 32.768 kHz oscillator output. On-chip timing functions include the MPU master clock, a real time clock (RTC), and the delta-sigma sample clock. In addition, the MPU has two general counter/timers. The ADC master clock, CKADC, is generated by an on-chip PLL. It multiplies the oscillator output frequency (CK32) by 150.
The CE clock frequency is always CK32 * 150, or 4.9152 MHz, where CK32 is the 32 kHz clock. The MPU clock frequency is determined by MPU_DIV and can be 4.9152 MHz *2-MPU_DIV Hz where MPU_DIV varies from 0 to 7 (MPU_DIV is 0 on power-up). This makes the MPU clock scalable from 4.9152 MHz down to 38.4 kHz. The circuit also generates a 2x MPU clock for use by the emulator. This 2x MPU clock is not generated when ECK_DIS is asserted by the MPU. The setting of MPU_DIV is maintained when the device transitions to BROWNOUT mode, but the time base in BROWNOUT mode is 28,672 Hz.
1.5.3 Real-Time Clock (RTC)
The RTC is driven directly by the crystal oscillator. It is powered by the either a battery or super capacitor that is connected to the VBAT pin. If the battery or super capacitor is not used, then the VBAT pin must be directly connected to the V3P3SYS pin. The RTC consists of a counter chain and output registers. The counter chain consists of seconds, minutes, hours, day of week, day of month, month, and year. The RTC is capable of processing leap years. Each counter has its own output register. Whenever the MPU reads the seconds register, all other output registers are automatically updated. Since the RTC clock is not coherent to the MPU clock, the MPU must read the seconds register until two consecutive reads are the same (requires either 2 or 3 reads). At this point, all RTC output registers will have the correct time. Regardless of the MPU clock speed, RTC reads require one wait state. RTC time is set by writing to the RTC registers in I/O RAM. Each byte written to RTC must be delayed at least 3 RTC cycles from any previous byte written to RTC. Hardware RTC write protection requires that a write to address 0x201F occur before each RTC write. Writing to address 0x201F opens a hardware `enable gate' that remains open until an RTC write occurs and then closes. It is not necessary to disable interrupts between the write operation to 0x201F and the RTC write because the `enable gate' will remain open until the RTC write finally occurs. Two time correction bits, RTC_DEC_SEC and RTC_INC_SEC are provided to adjust the RTC time. A pulse on one of these bits causes the time to be decremented or incremented by an additional second at the next update of the RTC_SEC register. Thus, if the crystal temperature coefficient is known, the MPU firmware can integrate temperature and correct the RTC time as necessary.
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78M6612 Data Sheet
1.5.4 Temperature Sensor
The device includes an on-chip temperature sensor for determining the temperature of the bandgap reference. The MPU may request an alternate multiplexer frame containing the temperature sensor output by asserting MUX_ALT. The primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system (see Section 3.3 Temperature Compensation).
1.5.5 Physical Memory
Flash Memory: The 78M6612 includes 32 KB of on-chip Flash memory. The Flash memory primarily contains MPU and CE program code. It also contains images of the CE DRAM, MPU RAM, and I/O RAM. On power-up, before enabling the CE, the MPU copies these images to their respective locations. Allocated Flash space for the CE program cannot exceed 1024 words (2 KB). The CE program must begin on a 1 KB boundary of the Flash address. The CE_LCTN[4:0] word defines which 1 KB boundary contains the CE code. Thus, the first CE instruction is located at 1024*CE_LCTN[4:0]. CE_LCTN must be defined before the CE is enabled. The Flash memory is segmented into 512 byte individually erasable pages. The CE engine cannot access its program memory when Flash write occurs. Thus, the Flash write procedure is to begin a sequence of Flash writes when CE_BUSY falls (CE_BUSY interrupt) and to make sure there is sufficient time to complete the sequence before CE_BUSY rises again. The actual time for the Flash write operation will depend on the exact number of cycles required by the CE program. Typically (CE program is 512 instructions, mux frame is 13 CK32 cycles), there will be 200 s of Flash write time, enough for 4 bytes of Flash write. If the CE code is shorter, there will be even more time. Two interrupts warn of collisions between the MPU firmware and the CE timing. If a Flash write is attempted while the CE is busy, the Flash write will not execute and the FW_COL0 interrupt will be issued. If a Flash write is still in progress when the CE would otherwise begin a code pass, the code pass is skipped, the write is completed, and the FW_COL1 interrupt is issued. The bit FLASH66Z (see Table 50) defines the speed for accessing Flash memory. To minimize supply current draw, this bit should be set to 1. Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence. These special pattern/sequence requirements prevent inadvertent erasure of the Flash memory. The mass erase sequence is: 1. Write 1 to the FLSH_MEEN bit (SFR address 0xB2[1]. 2. Write pattern 0xAA to FLSH_ERASE (SFR address 0x94). The mass erase cycle can only be initiated when the ICE port is enabled.
The page erase sequence is: 1. Write the page address to FLSH_PGADR (SFR address 0xB7[7:1]. 2. Write pattern 0x55 to FLSH_ERASE (SFR address 0x94). The MPU may write to the Flash memory. This is one of the non-volatile storage options available to the user in addition to external EEPROM. Rev. 1.2 41
78M6612 Data Sheet
DS_6612_001
FLSH_PWE (Flash program write enable) differentiates 80515 data store instructions (MOVX@DPTR,A) between Flash and XRAM writes. Updating individual bytes in Flash memory: The original state of a Flash byte is 0xFF (all ones). Once, a value other than 0xFF is written to a Flash memory cell, overwriting with a different value usually requires that the cell is erased first. Since cells cannot be erased individually, the page has to be copied to RAM, followed by a page erase. After this, the page can be updated in RAM and then written back to the Flash memory. MPU RAM: The 78M6612 includes 2k-bytes of static RAM memory on-chip (XRAM) plus 256-bytes of internal RAM in the MPU core. The 2K-bytes of static RAM are used for data storage during normal MPU operations. CE DRAM: The CE DRAM is the working data memory of the CE (128 32-bit words). The MPU can read and write the CE DRAM as the primary means of data communication between the two processors.
1.5.6 Optical Interface
The device includes an interface to implement an IR/optical port. The pin TX1 is designed to directly drive an external LED for transmitting data on an optical link. The pin RX1 is designed to sense the input from an external photo detector used as the receiver for the optical link. These two pins are connected to a dedicated UART port (UART1). The TX1 and RX1 pins can be inverted with configuration bits TX1INV and RX1INV, respectively. Additionally, the TX1 output may be modulated at 38 kHz. Modulation is available when system power is present (i.e. not in BROWNOUT mode). The TX1MOD bit enables modulation. Duty cycle is controlled by OPT_FDC[1:0], which can select 50%, 25%, 12.5%, and 6.25% duty cycle. 6.25% duty cycle means TX1 is low for 6.25% of the period. Figure 7 illustrates the TX1 generator.
VARPULSE WPULSE from OPT_TX UART OPT_TXINV OPT_TXMOD OPT_FDC A EN 2 OPT_TXMOD=1, OPT_FDC=2 (25%) A B 1/38kHz MOD DUTY DIO2 B
2 1 0 3
Internal OPT_TX
V3P3
OPT_TXE[1:0]
OPT_TXMOD=0 A B
Figure 7: Optical Interface When not needed for the optical UART, the TX1 pin can alternatively be configured as DIO2, WPULSE, or VARPULSE. The configuration bits are TX1E[1:0]. Likewise, RX1 can alternately be configured as DIO_1. Its control is RX1DIS.
42
Rev. 1.2
DS_6612_001
78M6612 Data Sheet
1.5.7 Digital I/O
The device includes up to 18 pins (QFN 68 package) or 16 pins (LQFP 64 package) of general purpose digital I/O. These pins are compatible with 5V inputs (no current-limiting resistors are needed). Some of them are dedicated DIO (DIO3), some are dual-function that can alternatively be used as LCD drivers (DIO4-11, 14-17, 19-21) and some share functions with the optical port (DIO1, DIO2). On reset or power-up, all DIO pins are inputs until they are configured for the desired direction under MPU control. The pins are configured by the DIO registers and by the five bits of the LCD_NUM register (located in I/O RAM). Once declared as DIO, each pin can be configured independently as an input or output with the DIO_DIRn bits. A 3-bit configuration word, DIO_Rx, can be used for certain pins, when configured as DIO, to individually assign an internal resource such as an interrupt or a timer control. Table 38 lists the direction registers and configurability associated with each group of DIO pins. Table 39 shows the configuration for a DIO pin through its associated bit in its DIO_DIR register. Tables showing the relationship between LCD_NUM and the available segment/DIO pins can be found in the Applications section and in Section 4.3 I/O Description under LCD_NUM[4:0]. Table 38: Data/Direction Registers and Internal Resources for DIO Pin Groups DIO Pin no. (64 LQFP) Pin no. (68 QFN) Data Register Direction Register Internal Resources Configurable x - - - - - 1 5 7 6 0 1 1 2 3 3 2 2 3 - 5 3 - 3 - Y Y Y Y Y Y Y Y Y 4 5 6 7 0 1 4 3 6 3 9 4 5 3 7 4 0 5 6 3 8 4 1 6 7 3 9 4 2 7 8 4 0 4 3 0 9 4 1 4 4 1 1 0 4 2 4 5 2 2 1 1 4 3 4 6 3 3 1 2 - - - - 1 3 - - - - 1 4 2 0 2 1 6 6 1 5 2 1 2 2 7 7
DIO1=P1 (SFR 0x90) DIO_DIR1 (SFR 0x91) Y Y - - - -
DIO Pin no. (64 LQFP) Pin no. (68 QFN) Data Register Direction Register Internal Resources Configurable
16 22 23 0 0
1 7 1 2 1 3 1 1
1 8 - - - -
1 9 2 3 2 4 3 3
2 0 4 4 4 7 4 4
2 1 - 6 8 5 5
2 2 -
2 3 -
- -
- -
DIO2=P2 (SFR 0xA0) DIO_DIR2 (SFR 0xA1) N N - N N N - -
Rev. 1.2
43
78M6612 Data Sheet Table 39: DIO_DIR Control Bit DIO_DIR [n] 0 DIO Pin n Function Input 1 Output
DS_6612_001
Additionally, if DIO6 and DIO7 are declared outputs, they can be configured as dedicated pulse outputs (WPULSE = DIO6, VARPULSE = DIO7) using DIO_PW and DIO_PV registers. In this case, DIO6 and DIO7 are under CE control. DIO4 and DIO5 can be configured to implement the EEPROM Interface. If the optical UART is not used, TX1 and RX1 can be configured as dedicated DIO pins (DIO1, DIO2, see Section 1.5.6 Optical Interface). A 3-bit configuration word, I/O RAM register, DIO_Rx (0x2009[2:0] through 0x200E[6:4]) can be used for certain pins, when configured as DIO, to individually assign an internal resource such as an interrupt or a timer control (see Table 38 for DIO pins available for this option). This way, DIO pins can be tracked even if they are configured as outputs. Tracking DIO pins configured as outputs is useful for pulse counting without external hardware.
When driving LEDs, relay coils etc., the DIO pins should sink the current into ground (as shown in Figure 8, right), not source it from V3P3D (as shown in Figure 8, left). This is due to the resistance of the internal switch that connects V3P3D to either V3P3SYS or VBAT. When configured as inputs, the dual-function (DIO/SEG) pins should not be pulled above V3P3SYS in MISSION and above VBAT in LCD and BROWNOUT modes. Doing so will distort the LCD waveforms of the other pins. This limitation applies to any pin that can be configured as a LCD driver. The control resources selectable for the DIO pins are listed in Table 40. If more than one input is connected to the same resource, the resources are combined using a logical OR.
78M6612 78M6612
V3P3SYS VBAT V3P3D DIO1
3.3V
V3P3SYS VBAT V3P3D DIO1
3.3V LED
R
LED DGND Not recommended DGND
R
Recommended
Figure 8: Connecting an External Load to DIO Pins
44
Rev. 1.2
DS_6612_001 Table 40: Selectable Controls using the DIO_DIR Bits DIO_R Value 0 1 2 3 4 5 6 7 Resource Selected for DIO Pin NONE Reserved T0 (counter0 clock) T1 (counter1 clock) High priority I/O interrupt (INT0 rising) Low priority I/O interrupt (INT1 rising) High priority I/O interrupt (INT0 falling) Low priority I/O interrupt (INT1 falling)
78M6612 Data Sheet
1.5.8 LCD Drivers
The device in the 68-pin QFN package contains 20 dedicated LCD segment drivers in addition to the 18 multi-use pins described above. Thus, the device is capable of driving between 80 to 152 pixels of LCD display with 25% duty cycle (or 60 to 114 pixels with 33% duty cycle). At eight pixels per digit, this corresponds to 10 to 19 digits. The device in the 64-pin LQFP package contains 18 dedicated LCD segment drivers in addition to the 17 multi-use pins described above. Thus, the device is capable of driving between 72 to 140 pixels of LCD display with 25% duty cycle (or 60 to 105 pixels with 33% duty cycle). At eight pixels per digit, this corresponds to 9 to 17 digits. The LCD drivers are grouped into four commons and up to 38 segment drivers (68-pin package), or 4 commons and 35 segment drivers (64-pin package). The LCD interface is flexible and can drive either digit segments or enunciator symbols. Segment drivers SEG18 and SEG19 can be configured to blink at either 0.5 Hz or 1 Hz. The blink rate is controlled by LCD_Y. There can be up to four pixels/segments connected to each of these drivers. LCD_BLKMAP18[3:0] and LCD_BLKMAP19[3:0] identify which pixels, if any, are to blink. LCD interface memory is powered by the non-volatile supply. The bits of the LCD memory are preserved in LCD and SLEEP modes, even if their pin is not configured as SEG. In this case, they can be useful as general- purpose non-volatile storage.
1.5.9 Battery Monitor
The battery voltage is measured by the ADC during alternative MUX frames if the BME (Battery Measure Enable) bit is set. While BME is set, an on-chip 45 k load resistor is applied to the battery and a scaled fraction of the battery voltage is applied to the ADC input. After each alternative MUX frame, the result of the ADC conversion is available at CE DRAM address 0x07. BME is ignored and assumed zero when system power is not available. See Section 5.4.4 Battery Monitor for details regarding the ADC LSB size and the conversion accuracy.
Rev. 1.2
45
78M6612 Data Sheet
DS_6612_001
1.5.10 EEPROM Interface
The 78M6612 provides hardware support for a two-pin or a three-pin EEPROM interface. The EEPROM interface uses the EECTRL and EEDATA registers for communication. 1.5.10.1 Two-Pin EEPROM Interface The dedicated 2-pin serial interface communicates with external EEPROM devices. The interface is multiplexed onto pins DIO4 (SCK) and DIO5 (SDA) controlled by the I/O RAM bits DIO_EEX[1:0] (see the I/O RAM Table). Set DIO_EEX[1:0] = 01 to select the two-wire EEPROM interface. The MPU communicates with the interface through two SFR registers: EEDATA and EECTRL. If the MPU wishes to write a byte of data to EEPROM, it places the data in EEDATA and then writes the `Transmit' command (CMD = 0011) to EECTRL. This initiates the transmit operation. The transmit operation is finished when the BUSY bit falls. Interrupt INT5 is also asserted when BUSY falls. The MPU can then check the RX_ACK bit to see if the EEPROM acknowledged the transmission. A byte is read by writing the Receive command (CMD[3:0] = 0001) to EECTRL and waiting for the BUSY bit to fall. Upon completion, the received data is in EEDATA. The serial transmit and receive clock is 78 kHz during each transmission, and the clock is held in a high state until the next transmission. The bits in EECTRL are shown in Table 41. The EEPROM interface can also be operated by controlling the DIO4 and DIO5 pins directly ("bit-banging"). However, controlling DIO4 and DIO5 directly is discouraged, because it may tie up the MPU to the point where it may become too busy to process interrupts. Table 41: EECTRL Status Bits Status Bit 7 6 5 4 Name ERROR BUSY RX_ACK TX_ACK Read / Write R R R R Reset State 0 0 1 1 Polarity Positive Positive Negative Negative Description 1 when an illegal command is received. 1 when serial data bus is busy. 0 indicates that the EEPROM sent an ACK bit. 0 indicates when an ACK bit has been sent to the EEPROM. CMD 0000 Operation No-op. Applying the no-op command will stop the I2C clock (SCK, DIO4). Failure to issue the no-op command will keep the SCK signal toggling. Receive a byte from EEPROM and send ACK. Transmit a byte to EEPROM. Issue a `STOP' sequence. Receive the last byte from EEPROM, do not send ACK. Issue a `START' sequence. No Operation, set the ERROR bit.
3-0
CMD[3:0]
W
0
Positive, see CMD Table
0001 0011 0101 0110 1001 Others
46
Rev. 1.2
DS_6612_001 1.5.10.2 3-Wire EEPROM Interface
78M6612 Data Sheet
A 500 kHz 3-wire interface, using SDATA, SCK, and a DIO pin for CS is available. The interface is selected with DIO_EEX[1:0] = 10. The same 2-wire EECTRL register is used, except the bits are reconfigured, as shown in Table 42. When EECTRL is written, up to 8 bits from EEDATA are either written to the EEPROM or read from the EEPROM, depending on the values of the EECTRL bits. Table 42: EECTRL Bits for 3-Wire Interface Control Bit Name Read/Write Description Wait for Ready. If this bit is set, the trailing edge of BUSY will be delayed until a rising edge is seen on the data line. This bit can be used during the last byte of a Write command to cause the INT5 interrupt to occur when the EEPROM has finished its internal write sequence. This bit is ignored if HiZ=0. Asserted while serial data bus is busy. When the BUSY bit falls, an INT5 interrupt occurs. Indicates that the SD signal is to be floated to high impedance immediately after the last SCK rising edge. Indicates that EEDATA is to be filled with data from EEPROM. Specifies the number of clocks to be issued. Allowed values are 0 through 8. If RD=1, CNT bits of data will be read MSB first, and right justified into the low order bits of EEDATA. If RD=0, CNT bits will be sent MSB first to EEPROM, shifted out of EEDATA's MSB. If CNT is zero, SDATA will simply obey the HiZ bit.
7
WFR
W
6 5 4
BUSY HiZ RD
R W W
3-0
CNT[3:0]
W
The timing diagrams in Figure 9 through Figure 13 describe the 3-wire EEPROM interface behavior. All commands begin when the EECTRL register is written. Transactions start by first raising the DIO pin that is connected to CS. Multiple 8-bit or less commands such as those shown in Figure 9 through Figure 13 are then sent via EECTRL and EEDATA. When the transaction is finished, CS must be lowered. At the end of a Read transaction, the EEPROM will be driving SDATA, but will transition to HiZ (high impedance) when CS falls. The firmware should then immediately issue a write command with CNT=0 and HiZ=0 to take control of SDATA and force it to a low-Z state.
EECTRL Byte Written CNT Cycles (6 shown) Write -- No HiZ SCLK (output) SDATA (output) SDATA output Z BUSY (bit)
D7 D6 D5 (LoZ) D4 D3 D2
INT5
Figure 9: 3-Wire Interface. Write Command, HiZ=0
Rev. 1.2
47
78M6612 Data Sheet
EECTRL Byte Written CNT Cycles (6 shown) Write -- With HiZ SCLK (output) SDATA (output) SDATA output Z BUSY (bit)
D7 D6 D5 (LoZ) D4 D3 D2 (HiZ)
DS_6612_001
INT5
Figure 10: 3-Wire Interface. Write Command, HiZ=1
EECTRL Byte Written CNT Cycles (8 shown) READ SCLK (output) SDATA (input) SDATA output Z BUSY (bit)
D7 D6 (HiZ) D5 D4 D3 D2 D1 D0
INT5
Figure 11: 3-Wire Interface. Read Command
EECTRL Byte Written Write -- No HiZ SCLK (output) SDATA (output) SDATA output Z BUSY (bit)
D7 (LoZ)
INT5 not issued CNT Cycles (0 shown)
EECTRL Byte Written Write -- HiZ SCLK (output) SDATA (output)
INT5 not issued CNT Cycles (0 shown)
SDATA output Z BUSY (bit)
(HiZ)
Figure 12: 3-Wire Interface. Write Command when CNT=0
EECTRL Byte Written CNT Cycles (6 shown) Write -- With HiZ and WFR SCLK (output) SDATA (out/in) SDATA output Z BUSY (bit)
D7 D6 D5 (From 6520) (LoZ) D4 D3 D2 BUSY (From EEPROM) (HiZ) READY
INT5
Figure 13: 3-Wire Interface. Write Command when HiZ=1 and WFR=1
48
Rev. 1.2
DS_6612_001
78M6612 Data Sheet
1.5.11 Hardware Watchdog Timer
V1 V3P3 V3P3 - 10mV V3P3 400mV Normal operation, WDT enabled VBIAS WDT disabled
In addition to the basic watchdog timer included in the 80515 MPU, an independent, robust, fixed-duration, watchdog timer (WDT) is included in the device. It uses the RTC crystal oscillator as its time base and must be refreshed by the MPU firmware at least every 1.5 seconds. When not refreshed on time the WDT overflows, and the part is reset as if the RESET pin were pulled high, except that the I/O RAM bits will be in the same state as after a wake-up from SLEEP or LCD modes (see Section 4.3 I/O RAM Description for a list of I/O RAM bit states after RESET and wake-up). 4100 oscillator cycles (or 125 ms) after the WDT overflow, the MPU will be launched from program address 0x0000. A status bit, WD_OVF, is set when WDT overflow occurs. This bit is powered by the non-volatile supply and can be read by the MPU to determine if the part is initializing after a WDT overflow event or after a power-up. After it is read, MPU firmware must clear WD_OVF. The WD_OVF bit is cleared by the RESET pin.
Battery modes
0V
There is no internal digital state that deactivates the WDT. For debug purposes, however, the WDT can be disabled by tying the V1 pin to V3P3 (see Figure 36). Of course, this also deactivates V1 power fault detection. Since there is no method in firmware to disable the crystal oscillator or the WDT, it is guaranteed that whatever state the part might find itself in, upon WDT overflow, the part will be reset to a known state.
Figure 14: Functions Defined by V1 Asserting ICE_E will also deactivate the WDT. This is the only method that will disable the WDT in BROWNOUT mode. In normal operation, the WDT is reset by periodically writing a one to the WDT_RST bit. The watchdog timer is also reset when the internal signal WAKE=0 (see Section 2.5 Wake Up Behavior).
1.5.12 Program Security
When enabled, the security feature limits the ICE to global Flash erase operations only. All other ICE operations are blocked. This guarantees the security of the user's MPU and CE program code. Security is enabled by MPU code that is executed in a 32 cycle preboot interval before the primary boot sequence begins. Once security is enabled, the only way to disable it is to perform a global erase of the Flash, followed by a chip reset. The first 32 cycles of the MPU boot code are called the preboot phase because during this phase the ICE is inhibited. A read-only status bit, PREBOOT, identifies these cycles to the MPU. Upon completion of preboot, the ICE can be enabled and is permitted to take control of the MPU. SECURE, the security enable bit, is reset whenever the chip is reset. Hardware associated with the bit permits only ones to be written to it. Thus, preboot code may set SECURE to enable the security feature but may not reset it. Once SECURE is set, the preboot code is protected and no external read of program code is possible,
Rev. 1.2
49
78M6612 Data Sheet Specifically, when SECURE is set: * * *
DS_6612_001
The ICE is limited to bulk Flash erase only. Page zero of Flash memory, the preferred location for the user's preboot code, may not be page-erased by either MPU or ICE. Page zero may only be erased with global Flash erase. Writes to page zero, whether by MPU or ICE are inhibited. The SECURE bit is to be used with caution! Inadvertently setting this bit will inhibit access to the part via the ICE interface, if no mechanism for actively resetting the part between reset and erase operations is provided.
1.5.13 Test Ports
TMUXOUT Pin: One out of 16 digital or 8 analog signals can be selected to be output on the TMUXOUT pin. The function of the multiplexer is controlled with the I/O RAM register TMUX (0x20AA[4:0]), as shown in Table 43. Table 43: TMUX[4:0] Selections TMUX[4:0] 0 1 2 3-5 6 7 8-0x0F 0x10 - 0x13 0x14 0x15 0x16 - 0x17 0x18 0x19 0x1A 0x1B 0x1C 0X1D 0X1E 0X1F Digital Digital Digital Digital - Digital Digital Digital Mode Analog Analog Analog Analog Analog Analog - - Digital Digital Function DGND Reserved DGND Reserved VBIAS Not used Reserved Not used RTM (Real time output from CE) WDTR_EN (Comparator 1 Output AND V1LT3) Not used RXD (from Optical interface, w/ optional inversion) MUX_SYNC CK_10M (10 MHz clock) CK_MPU (MPU clock) Reserved RTCLK (output of the oscillator circuit, nominally 32,786 Hz) CE_BUSY (busy interrupt generated by CE, 396 s) XFER_BUSY (transfer busy interrupt generated by CE, nominally every 999.7 ms)
50
Rev. 1.2
DS_6612_001
78M6612 Data Sheet
2 Functional Description
2.1 Theory of Operation
The energy delivered by a power source into a load can be expressed as:
E = V (t ) I (t )dt
0
t
Assuming phase angles are constant, the following formulae apply (for narrow band mode): P = Real Energy [Wh] = V * A * cos * t Q = Reactive Energy [VARh] = V * A * sin * t S = Apparent Energy [VAh] =
P2 + Q2
For actual measurement equations, refer to the applicable 78M6612 Firmware Description Document.
For a practical measurement, not only voltage and current amplitudes, but also phase angles and harmonic content may change constantly. Thus, simple RMS measurements are inherently inaccurate. A modern solid-state electricity Power and Energy Measurement IC such as the Teridian 78M6612 functions by emulating the integral operation above, i.e. it processes current and voltage samples through an ADC at a constant frequency. As long as the ADC resolution is high enough and the sample frequency is beyond the harmonic range of interest, the current and voltage samples, multiplied with the time period of sampling will yield an accurate quantity for the momentary energy. Summing up the momentary energy quantities over time will result in accumulated energy.
500 400 300 200 100 0 0 -100 -200
Current [A]
5
10
15
20
-300 -400 -500
Voltage [V] Energy per Interval [Ws] Accumulated Energy [Ws]
Figure 15: Voltage. Current, Momentary and Accumulated Energy Figure 15 shows the shapes of V(t), I(t), the momentary power and the accumulated power, resulting from 50 samples of the voltage and current signals over a period of 20 ms. The application of 240 VAC and 100 A results in an accumulation of 480 Ws (= 0.133 Wh) over the 20 ms period, as indicated by the Accumulated Power curve. The described sampling method works reliably, even in the presence of dynamic phase shift and harmonic distortion. Rev. 1.2 51
78M6612 Data Sheet
DS_6612_001
2.2
System Timing Summary
Figure 16 summarizes the timing relationships between the input MUX states, the CE_BUSY signal, and the two serial output streams. In this example, MUX_DIV[1:0] = 4 and FIR_LEN = 1 (384). The duration of each MUX frame is 1 + MUX_DIV[1:0] * 2 if FIR_LEN = 0 (288), and 1 + MUX_DIV[1:0] * 3 if FIR_LEN = 1 (384). An ADC conversion will always consume an integer number of CK32 clocks. Followed by the conversions is a single CK32 cycle where the bandgap voltage is allowed to recover from the change in CROSS. Each CE program pass begins when ADC0 (channel IA) conversion begins. Depending on the length of the CE program, it may continue running until the end of the ADC3 (VB) conversion. CE opcodes are constructed to ensure that all CE code passes consume exactly the same number of cycles. The result of each ADC conversion is inserted into the CE DRAM when the conversion is complete. The CE code is written to tolerate sudden changes in ADC data. The exact CK count when each ADC value is loaded into DRAM is shown in Figure 16. Figure 16 also shows that the serial RTM data stream begins transmitting at the beginning of state `S.' RTM, consisting of 140 CK cycles, will always finish before the next code pass starts.
ADC MUX Frame
ADC
CK32 150 MUX_SYNC MUX STATE ADC EXECUTION ADC0 S 0
MUX_DIV Conversions, MUX_DIV[1:0] = 01 (4 conversions) is shown
Settle
1
2
3
S
ADC1 900
ADC2 1350
ADC3 180 0 MAX CK COUNT
CE
CE_EXECUTION
0
450
CK COUNT = CE_CYCLES + floor((CE_CYCLES + 2) / 5) CE_BUSY XFER_BUSY INITIATED BY A CE OPCODE AT END OF SUM INTERVAL
RTM TIMING
RTM NOTES: 1. ALL DIMENSIONS ARE 5MHZ CK COUNTS. 2. THE PRECISE FREQUENCY OF CK IS 150*CRYSTAL FREQUENCY = 4.9152MHz. 3. XFER_BUSY OCCURS ONCE EVERY (PRESAMPS * SUM_CYCLES) CODE PASSES.
140
Figure 16: Timing Relationship between ADC MUX, Compute Engine, and Serial Transfers
CK32 MUX_SYNC CKTEST TMUXOUT/RTM
LSB
0
1
30
31
LSB
0
1
30
SIG N
31
LSB
0
1
30
31
LSB
0
1
30
31
SIG N
SIG N
RTM DATA0 (32 bits) RTM DATA1 (32 bits) RTM DATA2 (32 bits) RTM DATA3 (32 bits)
Figure 17: RTM Output Format 52 Rev. 1.2
SIG N
FLAG
FLAG
FLAG
FLAG
DS_6612_001
78M6612 Data Sheet
2.3
Battery Modes
Shortly after system power (V3P3SYS) is applied, the part will be in MISSION mode. MISSION mode means that the part is operating with system power and that the internal PLL is stable. This mode is the normal operation mode where the part is capable of measuring energy. When system power is not available (i.e. when V1Rev. 1.2
53
78M6612 Data Sheet Table 44: Available Circuit Functions Circuit Function CE CE Data RAM FIR Analog circuits: PLL, ADC, VREF, BME etc MPU clock rate MPU_DIV ICE DIO Pins Watchdog Timer LCD EEPROM Interface (2-wire) EEPROM Interface (3-wire) UART Optical TX modulation Flash Read Flash Page Erase Flash Write RAM Read and Write Wakeup Timer Oscillator and RTC DRAM data preservation V3P3D voltage output pin "--" means "not active. System Power MISSION Yes Yes Yes Yes 4.92 MHz (from PLL) Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
DS_6612_001
Battery Power (Non-volatile Supply) BROWNOUT - Yes - - 28.672 kHz (7/8 of 32768 Hz) - Yes Yes Yes Yes Yes (8kb/s) Yes (16kb/s) Yes - Yes Yes - Yes Yes Yes Yes Yes - - - - - Yes - - - - - - - - Yes Yes - - - - - - - - - - - - - - - - Yes Yes - - LCD - - - - SLEEP - - - -
2.3.1 BROWNOUT Mode
In BROWNOUT mode, most non-measurement digital functions, as shown in Table 44, are active, including ICE, UART, EEPROM, LCD, and RTC. In BROWNOUT mode, a low bias current regulator will provide 2.5 Volts to V2P5 and V2P5NV. The regulator has an output called BAT_OK to indicate that it has sufficient overhead. When BAT_OK = 0, the part will enter SLEEP mode. From BROWNOUT mode, the MPU can voluntarily enter LCD or SLEEP modes. When system power is restored, the part will automatically transition from any of the battery modes to mission mode, once the PLL has settled. The MPU will run at crystal clock rate in BROWNOUT. The value of MPU_DIV will be remembered (not changed) as the part enters and exits BROWNOUT. MPU_DIV will be ignored during BROWNOUT.
54
Rev. 1.2
DS_6612_001
78M6612 Data Sheet
While PLL_OK = 0, the I/O RAM bits ADC_E and CE_E are held in zero state disabling both ADC and CE. When PLL_OK falls, the CE program counter is cleared immediately and all FIR processing halts. Figure 19 shows the functional blocks active in BROWNOUT mode.
MISSION
V3P3SYS falls IE_PLLRISE V3P3SYS rises IE_PLLFALL
RESET
V1 > VBIAS V1 <= VBIAS
V3P3SYS rises LCD_ONLY
BROWNOUT
V3P3SYS rises RESET & VBAT_OK IE_WAKE SLEEP or timer VBAT_OK
LCD
timer
VBAT_OK RESET & VBAT_OK
VBAT_OK
SLEEP
Figure 18: Operation Modes State Diagram
2.3.2 LCD Mode
In LCD mode, the data contained in the LCD_SEG registers is displayed, i.e. up to four LCD segments connected to each of the pins SEG18 and SEG19 can be made to blink without the involvement of the MPU, which is disabled in LCD mode. This mode can be exited only by system power up or by a timeout of the wake-up timer. Figure 20 shows the functional blocks active in LCD mode.
2.3.3 SLEEP Mode
In SLEEP mode, the battery current is minimized and only the Oscillator and RTC functions are active. This mode can be exited only by system power-up or by a timeout of the wake-up timer. Figure 21 shows the functional blocks active in SLEEP mode.
Rev. 1.2
55
78M6612 Data Sheet
VREF V3P3A GNDA V3P3SYS
DS_6612_001
IA VA IB VB
VBAT
ADC CONVERTER MUX VBIAS VBIAS
V3P3D
V3P3A
+ ADC_E FIR VBAT FIR_LEN
V3P3D
TEMP MUX MUX CTRL EQU MUX_ALT CHOP_E MUX_DIV OSC (32KHz)
VREF VREF_CAL VREF_DIS CROSS CK32 VREF
VBAT
VOLT REG
XIN XOUT CKTEST/ SEG19
RTCLK (32KHz)
MCK PLL
CK32 32KHz
DIV ADC
LCD_ONLY SLEEP
GNDD V2P5
CKOUT_E 4.9MHz CKOUT_E CK_GEN ECK_DIS MPU_DIV MUX_SYNC CKCE <4.9MHz STRT CE 32 bit Compute Engine CK_2X
CKADC 4.9MHz
CKFIR 4.9MHz V3P3D LCD_GEN CE RAM (0.5KB) VLC2 VLC1 LCD_MODE LCD_E LCD DISPLAY DRIVER MEMORY SHARE LCD_NUM LCD_MODE LCD_CLK LCD_E LCD_BLKMAP LCD_SEG LCD_Y DIGITAL I/O DIO_EEX DIO_PV/PW DIO_DIR DIO_R LCD_NUM DIO RTC RTC_DEC_SEC RTC_INC_SEC CONFIGURATION PARAMETERS VLC0 2.5V to logic
WPULSE VARPULSE RTM DATA 00-7F
MUX
(SEG13 and SEG 14 on 68 Pin Package Only)
TEST
TEST MODE
COM0..3 SEG0..18
SEG32,33 SEG19,38
CE CONTROL RTM_0..3 RTM_E CE_E
PROG 000-7FF
1000-11FF
SEG24/DIO4 .. SEG31/DIO11 SEG34/DIO14 .. SEG37/DIO17, SEG39/DIO19, SEG40/DIO20
XFER BUSY
CE_BUSY
I/O RAM
PLS_INV PLS_INTERVAL PLS_MAXWIDTH CE_LCTN EQU PRE_SAMPS SUM_CYCLES
WPULSE VARPULSE EEPROM INTERFACE
DIO1,2
RTCLK
CKMPU <4.9MHz SDCK SDOUT UART SDIN MPU (80515) DATA 0000-FFFF 0000-07FF 2000-20FF
RX TX
RX1/ DIO1
OPTICAL
CONFIG
(68 Pin Package Only)
DIO3, DIO21/SEG41
MPU XRAM (2KB)
TX1/ DIO2/ WPULSE/ VARPULSE
MOD OPT_TXMOD OPT_FDC VBIAS
OPT_RXDIS OPT_RXINV OPT_TXE OPT_TXINV
PROG 0000-7FFF
MEMORY SHARE CE_LCTN
00007FFF
FLASH (32KB) FLSH66ZT
MPU_RSTZ POWER FAULT WAKE FAULTZ COMP_STAT
V1
EMULATOR PORT E_RXTX E_TCLK E_RST (Open Drain) TEST MUX TMUX[4:0]
TMUXOUT
RESET
E_RXTX/SEG38 E_TCLK/SEG33 E_RST/SEG32
ICE_E
January 14, 2009
Figure 19: Functional Blocks in BROWNOUT Mode (inactive blocks grayed out)
56
Rev. 1.2
DS_6612_001
VREF V3P3A GNDA
78M6612 Data Sheet
V3P3SYS
IA VA IB VB
VBAT
ADC CONVERTER MUX VBIAS VBIAS
V3P3D
V3P3A
+ ADC_E FIR VBAT FIR_LEN
V3P3D
TEMP MUX MUX CTRL EQU MUX_ALT CHOP_E MUX_DIV OSC (32KHz)
VREF VREF_CAL VREF_DIS CROSS CK32 VREF
VBAT
VOLT REG
XIN XOUT CKTEST/ SEG19
RTCLK (32KHz)
MCK PLL
CK32 32KHz
DIV ADC
LCD_ONLY SLEEP
GNDD V2P5
CKOUT_E 4.9MHz CKOUT_E CK_GEN ECK_DIS MPU_DIV MUX_SYNC CKCE <4.9MHz STRT CE 32 bit Compute Engine CK_2X
CKADC 4.9MHz
CKFIR 4.9MHz V3P3D LCD_GEN CE RAM (0.5KB) VLC2 VLC1 LCD_MODE LCD_E LCD DISPLAY DRIVER MEMORY SHARE LCD_NUM LCD_MODE LCD_CLK LCD_E LCD_BLKMAP LCD_SEG LCD_Y DIGITAL I/O DIO_EEX DIO_PV/PW DIO_DIR DIO_R LCD_NUM DIO RTC RTC_DEC_SEC RTC_INC_SEC CONFIGURATION PARAMETERS VLC0 2.5V to logic
WPULSE VARPULSE RTM DATA 00-7F
MUX
(SEG13 and SEG 14 on 68 Pin Package Only)
TEST
TEST MODE
COM0..3 SEG0..18
SEG32,33 SEG19,38
CE CONTROL RTM_0..3 RTM_E CE_E
PROG 000-7FF
1000-11FF
SEG24/DIO4 .. SEG31/DIO11 SEG34/DIO14 .. SEG37/DIO17, SEG39/DIO19, SEG40/DIO20
XFER BUSY
CE_BUSY
I/O RAM
PLS_INV PLS_INTERVAL PLS_MAXWIDTH CE_LCTN EQU PRE_SAMPS SUM_CYCLES
WPULSE VARPULSE EEPROM INTERFACE
DIO1,2
RTCLK
CKMPU <4.9MHz SDCK SDOUT UART SDIN MPU (80515) DATA 0000-FFFF 0000-07FF 2000-20FF
RX TX
RX1/ DIO1
OPTICAL
CONFIG
(68 Pin Package Only)
DIO3, DIO21/SEG41
MPU XRAM (2KB)
TX1/ DIO2/ WPULSE/ VARPULSE
MOD OPT_TXMOD OPT_FDC VBIAS
OPT_RXDIS OPT_RXINV OPT_TXE OPT_TXINV
PROG 0000-7FFF
MEMORY SHARE CE_LCTN
00007FFF
FLASH (32KB) FLSH66ZT
MPU_RSTZ POWER FAULT WAKE FAULTZ COMP_STAT
V1
EMULATOR PORT E_RXTX E_TCLK E_RST (Open Drain) TEST MUX TMUX[4:0]
TMUXOUT
RESET
E_RXTX/SEG38 E_TCLK/SEG33 E_RST/SEG32
ICE_E
January 14, 2009
Figure 20: Functional Blocks in LCD Mode (inactive blocks grayed out)
Rev. 1.2
57
78M6612 Data Sheet
VREF V3P3A GNDA V3P3SYS
DS_6612_001
IA VA IB VB
VBAT
ADC CONVERTER MUX VBIAS VBIAS
V3P3D
V3P3A
+ ADC_E FIR VBAT FIR_LEN
V3P3D
TEMP MUX MUX CTRL EQU MUX_ALT CHOP_E MUX_DIV OSC (32KHz)
VREF VREF_CAL VREF_DIS CROSS CK32 VREF
VBAT
VOLT REG
XIN XOUT CKTEST/ SEG19
RTCLK (32KHz)
MCK PLL
CK32 32KHz
DIV ADC
LCD_ONLY SLEEP
GNDD V2P5
CKOUT_E 4.9MHz CKOUT_E CK_GEN ECK_DIS MPU_DIV MUX_SYNC CKCE <4.9MHz STRT CE 32 bit Compute Engine CK_2X
CKADC 4.9MHz
CKFIR 4.9MHz V3P3D LCD_GEN CE RAM (0.5KB) VLC2 VLC1 LCD_MODE LCD_E LCD DISPLAY DRIVER MEMORY SHARE LCD_NUM LCD_MODE LCD_CLK LCD_E LCD_BLKMAP LCD_SEG LCD_Y DIGITAL I/O DIO_EEX DIO_PV/PW DIO_DIR DIO_R LCD_NUM DIO RTC RTC_DEC_SEC RTC_INC_SEC CONFIGURATION PARAMETERS VLC0 2.5V to logic
WPULSE VARPULSE RTM DATA 00-7F
MUX
(SEG13 and SEG 14 on 68 Pin Package Only)
TEST
TEST MODE
COM0..3 SEG0..18
SEG32,33 SEG19,38
CE CONTROL RTM_0..3 RTM_E CE_E
PROG 000-7FF
1000-11FF
SEG24/DIO4 .. SEG31/DIO11 SEG34/DIO14 .. SEG37/DIO17, SEG39/DIO19, SEG40/DIO20
XFER BUSY
CE_BUSY
I/O RAM
PLS_INV PLS_INTERVAL PLS_MAXWIDTH CE_LCTN EQU PRE_SAMPS SUM_CYCLES
WPULSE VARPULSE EEPROM INTERFACE
DIO1,2
RTCLK
CKMPU <4.9MHz SDCK SDOUT UART SDIN MPU (80515) DATA 0000-FFFF 0000-07FF 2000-20FF
RX TX
RX1/ DIO1
OPTICAL
CONFIG
(68 Pin Package Only)
DIO3, DIO21/SEG41
MPU XRAM (2KB)
TX1/ DIO2/ WPULSE/ VARPULSE
MOD OPT_TXMOD OPT_FDC VBIAS
OPT_RXDIS OPT_RXINV OPT_TXE OPT_TXINV
PROG 0000-7FFF
MEMORY SHARE CE_LCTN
00007FFF
FLASH (32KB) FLSH66ZT
MPU_RSTZ POWER FAULT WAKE FAULTZ COMP_STAT
V1
EMULATOR PORT E_RXTX E_TCLK E_RST (Open Drain) TEST MUX TMUX[4:0]
TMUXOUT
RESET
E_RXTX/SEG38 E_TCLK/SEG33 E_RST/SEG32
ICE_E
January 14, 2009
Figure 21: Functional Blocks in SLEEP Mode (inactive blocks grayed out)
58
Rev. 1.2
DS_6612_001
System Power (V3P3SYS)
78M6612 Data Sheet
V1_OK Battery Current
300nA
MPU Mode
BROWNOUT
Transition
MISSION
WAKE
13..14 CK cycles PLL (4.2MHz/MUX_DIV) 2048...4096 CK32 cycles
MPU Clock Source
Xtal
PLL_OK
time
Figure 22: Transition from BROWNOUT to MISSION Mode when System Power Returns
V3P3SYS and VBAT
V1_OK Battery Current BROWNOUT Xtal
300nA
MPU Mode
MISSION
MPU Clock Source
PLL (4.2MHz)
WAKE
14.5 CK32 cycles 4096 CK32 cycles
PLL_OK
Internal RESETZ
1024 CK32 cycles
time
Figure 23: Power-Up Timing with V3P3SYS and VBAT Tied Together
Rev. 1.2
59
78M6612 Data Sheet
DS_6612_001
VBAT
Battery Current
MPU Mode
BROWNOUT
MPU Clock Source
Xtal
WAKE
14.5 CK32 cycles
PLL_OK
Internal RESETZ
1024 CK32 cycles
VBAT_OK time
Figure 24: Power-Up Timing with VBAT Only
2.4
Fault and Reset Behavior
Reset Mode: When the RESET pin is pulled high all digital activity stops. The oscillator and RTC module continue to run. Additionally, all I/O RAM bits are set to their default states. As long as V1, the input voltage at the power fault block, is greater than VBIAS, the internal 2.5 V regulator will continue to provide power to the digital section. Once initiated, the reset mode will persist until the reset timer times out, signified by the internal signal WAKE rising. This will occur in 4100 cycles of the real time clock after RESET goes low, at which time the MPU will begin executing its preboot and boot sequences from address 00. See Section 1.5.12 Program Security for more description of preboot and boot. If system power is not present, the reset timer duration will be 2 cycles of the crystal clock, at which time the MPU will begin executing in BROWNOUT mode, starting at address 00. Power Fault Circuit: The 78M6612 includes a comparator to monitor system power fault conditions. When the output of the comparator falls (V160
Rev. 1.2
DS_6612_001
78M6612 Data Sheet
If there is no battery when system power returns, the part will switch to mission mode when PLL_OK rises. All configuration bits will be in reset state, and RTC and MPU RAM data will be unknown and must be initialized by the MPU.
2.5
Wake Up Behavior
As described above, the 78M6612 will always wake up in mission mode when system power is restored. Additionally, the part will wake up in BROWNOUT mode when a timeout of the wake-up timer occurs.
2.5.1 Wake on Timer
If the part is in SLEEP or LCD mode, it can be awakened by the wake-up timer. Until this timer times out, the MPU is in reset due to WAKE being low. When the wake-up timer times out, the WAKE signal rises and within three crystal cycles, the MPU begins to execute. The MPU can determine whether the timer woke it by checking the AUTOWAKE interrupt flag (IE_WAKE). The wake-up timer begins timing when the part enters LCD or SLEEP mode. Its duration is controlled by WAKE_PRD[2:0] and WAKE_RES. WAKE_RES selects a timer LSB of either 1 minute (WAKE_RES=1) or 2.5 seconds (WAKE_RES=0). WAKE_PRD[2:0] selects a duration of from 1 to 7 LSBs. The timer is armed by WAKE_ARM=1. It must be armed at least three RTC cycles before SLEEP or LCD_ONLY is initiated. Setting WAKE_ARM presets the timer with the values in WAKE_RES and WAKE_PRD and readies the timer to start when the MPU writes to SLEEP or LCD_ONLY. The timer is reset and disarmed whenever the MPU is awake. Thus, if it is desired to wake the MPU periodically (every 5 seconds, for example) the timer must be rearmed every time the MPU is awakened.
2.6
Data Flow
The data flow between CE and MPU is shown in Figure 25. In a typical application, the 32-bit compute engine (CE) sequentially processes the samples from the voltage inputs on pins IA, VA, IB, and VB, performing calculations to measure active power (Wh), reactive power (VARh), A2h, and V2h for fourquadrant measurement. These measurements are then accessed by the MPU, processed further and output using the peripheral devices available to the MPU.
Pulses
IRQ
Samples
CE
PreProcessor
Data
MPU
PostProcessor
Processed Metering Data
I/O RAM (Configuration RAM)
Figure 25: MPU/CE Data Flow
Rev. 1.2
61
78M6612 Data Sheet
DS_6612_001
2.7
CE/MPU Communication
Figure 26 shows the functional relationship between CE and MPU. The CE is controlled by the MPU via shared registers in the I/O RAM and by registers in the CE DRAM. The CE outputs two interrupt signals to the MPU: CE_BUSY and XFER_BUSY, which are connected to the MPU interrupt service inputs as external interrupts. CE_BUSY indicates that the CE is actively processing data. This signal will occur once every multiplexer cycle. XFER_BUSY indicates that the CE is updating data to the output region of the CE DRAM. This will occur whenever the CE has finished generating a sum by completing an accumulation interval determined by SUM_CYCLES * PRE_SAMPS samples. Interrupts to the MPU occur on the falling edges of the XFER_BUSY and CE_BUSY signals.
PULSES
VAR (DIO7) W (DIO6)
VARSUM
WSUM
APULSEW APULSER EXT_PULSE SAG CONTROL
DISPLAY (memory-mapped LCD segments) SERIAL (UART0/1)
MPU
EEPROM (I2C) DIO
ADC
SAMPLES
DATA
CE_BUSY XFER_BUSY
CE
Mux Ctrl.
INTERRUPTS
I/O RAM (CONFIGURATION RAM)
Figure 26: MPU/CE Communication
62
Rev. 1.2
DS_6612_001
78M6612 Data Sheet
3 Application Information
3.1 Connection of Sensors (CT, Resistive Shunt)
Figure 27 and Figure 28 show how resistive dividers, current transformers, and restive shunts are connected to the voltage and current inputs of the 78M6612.
Figure 27: Resistive Voltage Divider (Left), Current Transformer (Right)
Figure 28: Resistive Shunt
Rev. 1.2
63
78M6612 Data Sheet
DS_6612_001
3.2
Temperature Measurement
Measurement of absolute temperature uses the on-chip temperature sensor while applying the following formula:
T=
( N (T ) - N n ) + Tn Sn
In the above formula, T is the temperature in C, N(T) is the ADC count at temperature T, N n is the ADC count at 25C, S n is the sensitivity in LSB/C as stated in the Electrical Specifications, and T n is +25C. Example: At 25C a temperature sensor value of 518,203,584 (N n ) is read by the ADC by a 78M6612 in the 64-pin LQFP package. At an unknown temperature T the value 449.648.000 is read at (N(T)). The absolute temperature is then determined by dividing both N n and N(T) by 512 to account for the 9-bit shift of the ADC value and then inserting the results into the above formula, using -2220 for LSB/C:
T=
449.648.000 - 518,203,584 + 25C = 85.3C 512 (-2220)
It is recommended to base temperature measurements on TEMP_RAW_X which is the sum of two consecutive temperature readings thus being higher by a factor of two than the raw sensor readings.
3.3
Temperature Compensation
Temperature Coefficients: The internal voltage reference is calibrated during device manufacture. The temperature coefficients TC1 and TC2 are given as constants that represent typical component behavior (in V/C and V/C2, respectively). Since TC1 and TC2 are given in V/C and V/C2, respectively, the value of the VREF voltage (1.195V) has to be taken into account when transitioning to PPM/C and PPM/C2. This means that PPMC = 26.84*TC1/1.195, and PPMC2 = 1374*TC2/1.195). Temperature Compensation: The CE provides the bandgap temperature to the MPU, which then may digitally compensate the power outputs for the temperature dependence of VREF, using the CE register GAIN_ADJ. Since the band gap amplifier is chopper-stabilized via the CHOP_EN bits, the most significant long-term drift mechanism in the voltage reference is removed. The MPU, not the CE, is entirely in charge of providing temperature compensation. The MPU applies the following formula to determine GAIN_ADJ (address 0x12). In this formula TEMP_X is the deviation from nominal or calibration temperature expressed in multiples of 0.1C:
GAIN _ ADJ = 16385 +
TEMP _ X PPMC TEMP _ X 2 PPMC 2 + 214 2 23
In a power and energy measurement unit, the 78M6612 is not the only component contributing to temperature dependency. A whole range of components (e.g. current transformers, resistor dividers, power sources, filter capacitors) will contribute temperature effects. Since the output of the on-chip temperature sensor is accessible to the MPU, temperaturecompensation mechanisms with great flexibility are possible. MPU access to GAIN_ADJ permits a system-wide temperature correction over the entire unit rather than local to the chip.
64
Rev. 1.2
DS_6612_001
78M6612 Data Sheet
3.4
Temperature Compensation and Mains Frequency Stabilization for the RTC
The flexibility provided by the MPU allows for compensation of the RTC using the substrate temperature. To achieve this, the crystal has to be characterized over temperature and the three coefficients Y_CAL, Y_CALC, and Y_CAL_C2 have to be calculated. Provided the IC substrate temperatures tracks the crystal temperature the coefficients can be used in the MPU firmware to trigger occasional corrections of the RTC seconds count, using the RTC_DEC_SEC or RTC_INC_SEC registers in I/O RAM. Example: Let us assume a crystal characterized by the measurements shown in Table 45. Table 45: Frequency over Temperature Deviation from Nominal Temperature [C] +50 +25 0 -25 -50 Measured Frequency [Hz] 32767.98 32768.28 32768.38 32768.08 32767.58 Deviation from Nominal Frequency [PPM] -0.61 8.545 11.597 2.441 -12.817
The values show that even at nominal temperature (the temperature at which the chip was calibrated for energy), the deviation from the ideal crystal frequency is 11.6 PPM, resulting in about one second inaccuracy per day, i.e. more than some standards allow. As Figure 29 shows, even a constant compensation would not bring much improvement, since the temperature characteristics of the crystal are a mix of constant, linear, and quadratic effects.
32768.5 32768.4 32768.3 32768.2 32768.1 32768 32767.9 32767.8 32767.7 32767.6 32767.5 -50 -25 0 25 50
Figure 29: Crystal Frequency over Temperature One method to correct the temperature characteristics of the crystal is to obtain coefficients from the curve in Figure 29 by curve-fitting the PPM deviations. A fairly close curve fit is achieved with the coefficients a = 10.89, b = 0.122, and c = -0.00714 (see Figure 30).
a b c f = f nom 1 + 6 + T 6 + T 2 6 10 10 10
When applying the inverted coefficients, a curve (see Figure 30) will result that effectively neutralizes the original crystal characteristics.
Rev. 1.2
65
78M6612 Data Sheet
32768.5 32768.4 32768.3 32768.2 32768.1 32768 32767.9 32767.8 32767.7 32767.6 32767.5 -50 -25 0 25 50 crystal curve fit inverse curve
DS_6612_001
Figure 30: Crystal Compensation The MPU Demo Code supplied with the Teridian Demo Kits has a direct interface for these coefficients and it directly controls the RTC_DEC_SEC or RTC_INC_SEC registers. The Demo Code uses the coefficients in the form:
CORRECTION ( ppm) =
Y _ CAL Y _ CALC Y _ CALC 2 +T +T2 10 100 1000
Note that the coefficients are scaled by 10, 100, and 1000 to provide more resolution. For our example case, the coefficients would then become (after rounding): Y_CAL = 109, Y_CALC = 12, Y_CALC2 = 7 Alternatively, the mains frequency may be used to stabilize or check the function of the RTC. For this purpose, the CE provides a count of the zero crossings detected for the selected line voltage in the MAIN_EDGE_X address. This count is equivalent to twice the line frequency, and can be used to synchronize and/or correct the RTC.
3.5
Connecting 5V Devices
All digital input pins of the 78M6612 are compatible with external 5V devices. I/O pins configured as inputs do not require current-limiting resistors when they are connected to external 5V devices.
66
Rev. 1.2
DS_6612_001
78M6612 Data Sheet
3.6
Connecting LCDs
The 78M6612 has a LCD controller on-chip capable of controlling static or multiplexed LCDs. Figure 31 shows the basic connection for a LCD.
78M6612
LCD
segments
commons
Figure 31: Connecting LCDs The LCD segment pins can be organized in the following groups: 1. Seventeen pins are dedicated LCD segment pins (SEG0 to SEG13, SEG16 to SEG18). 2. Four pins are dual-function pins CKTEST/SEG19, E_RXTX/SEG38, E_TCLK/SEG33, and E_RST/SEG32. 3. Fourteen pins are available as combined DIO and segment pins SEG24/DIO4 to SEG31/DIO11, SEG34/DIO14 to SEG37/DIO17, SEG39/DIO19, and SEG40/DIO20. 4. The QFN-68 package adds an additional combination pin, SEG41/DIO21. Also adds two additional LCD segment pins, SEG13 and SEG14. The split between DIO and LCD use of the combined pins is controlled with the DIO register LCD_NUM. LCD_NUM can be assigned any number between 0 and 18. The first dual-purpose pin to be allocated as LCD is SEG41/DIO21 (on the 68-pin QFN package). Thus if LCD_NUM=2, SEG41 and SEG 40 will be configured as LCD. The remaining SEG39 to SEG24 will be configured as DIO19 to DIO4. DIO1 and DIO2 are always available, if not used for UART1. Note that pins CKTEST/SEG19, E_RXTX/SEG38, E_TCLK/SEG33, and E_RST/SEG32 are not affected by LCD_NUM. Table 46 and Table 47 show the allocation of DIO and segment pins as a function of LCD_NUM for both package types.
Rev. 1.2
67
78M6612 Data Sheet
DS_6612_001
Table 46: LCD and DIO Pin Assignment by LCD_NUM for the QFN-68 Package SEG in Addition to SEG0-SEG18 None 41 40-41 39-41 39-41 37, 39-41 36-37, 39-41 35-37, 39-41 34-37, 39-41 34-37, 39-41 34-37, 39-41 31, 34-37, 39-41 30-31, 34-37, 39-41 29-31, 34-37, 39-41 28-31, 34-37, 39-41 27-31, 34-37, 39-41 26-31, 34-37, 39-41 25-31, 34-37, 39-41 24-31, 34-37, 39-41 Total Number of LCD Segment Pins Including SEG0-SEG18 19 20 21 22 22 23 24 25 26 26 26 27 28 29 30 31 32 33 34 DIO Pins in Addition to DIO1DIO2 4-11,14-17, 19-21 4-11, 14-17, 19-20 4-11, 14-17, 19 4-11, 14-17 4-11, 14-17 4-11, 14-16 4-11, 14-15 4-11, 14 4-11 4-11 4-11 4-10 4-9 4-8 4-7 4-6 4-5 4 None Total Number of DIO Pins Including DIO1, DIO2 18 17 16 15 15 14 13 12 11 11 11 10 9 8 7 6 5 4 3
LCD_NUM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Note: LCD segment numbers are given without CKTEST/SEG19, E_RXTX/SEG38, E_TCLK/SEG33, and E_RST/SEG32.
68
Rev. 1.2
DS_6612_001
78M6612 Data Sheet
Table 47: LCD and DIO Pin Assignment by LCD_NUM for the LQFP-64 Package SEG in Addition to LCD_NUM SEG0-SEG18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - - 40 39, 40 39, 40 37, 39, 40 36-37, 39, 40 35-37, 39, 40 34-37, 39, 40 34-37, 39, 40 34-37, 39, 40 31, 34-37, 39, 40 30-31, 34-37, 39, 40 29-31, 34-37, 39, 40 28-31, 34-37, 39, 40 27-31, 34-37, 39, 40 26-31, 34-37, 39, 40 25-31, 34-37, 39, 40 24-31, 34-37, 39, 40 Total Number of LCD Segment Pins Including SEG0SEG18 17 17 18 19 19 20 21 22 23 23 23 24 25 26 27 28 29 30 31 DIO Pins in Addition to DIO1DIO2 4-11, 14-17, 19, 20 4-11, 14-17, 19, 20 4-11, 14-17, 19 4-11, 14-17 4-11, 14-17 4-11, 14-16 4-11, 14-15 4-11, 14 4-11 4-11 4-11 4-10 4-9 4-8 4-7 4-6 4-5 4 None Total Number of DIO Pins Including DIO1, DIO2 16 16 15 14 14 13 12 11 10 10 10 9 8 7 6 5 4 3 2
Note: LCD segment numbers are given without CKTEST/SEG19, E_RXTX/SEG38, E_TCLK/SEG33, and E_RST/SEG32. Note: SEG14 and SEG15 are not available in the 64-pin package.
3.7
Connecting I C EEPROMs
2
I2C EEPROMs or other I2C compatible devices should be connected to the DIO pins DIO4 and DIO5, as shown in Figure 32. Pull-up resistors of roughly 10 k to V3P3D (to ensure operation in BROWNOUT mode) should be used for both SCL and SDA signals. The DIO_EEX register in I/O RAM must be set to 01 in order to convert the DIO pins DIO4 and DIO5 to I2C pins SCL and SDA.
Rev. 1.2
69
78M6612 Data Sheet
V3P3D 10k 78M6612 DIO4 DIO5 10k EEPROM SCL SDA
DS_6612_001
. Figure 32: I C EEPROM Connection
2
3.8
Connecting 3-Wire EEPROMs
Wire EEPROMs and other compatible devices should be connected to the DIO pins DIO4 and DIO5, as
shown in Figure 33. DIO5 connects to both the DI and DO pins of the three-wire device. The CS pin must be connected to a vacant DIO pin of the 78M6612. A pull-up resistor of roughly 10 k to V3P3D (to ensure operation in BROWNOUT mode) should be used for the DI/DO signals, and the CS pin should be pulled down with a resistor to prevent that the 3-wire device is selected on power-up, before the 78M6612 can establish a stable signal for CS. The DIO_EEX register in I/O RAM must be set to 10 in order to convert the DIO pins DIO4 and DIO5 to Wire pins. The pull-up resistor for DIO5 may not be necessary.
78M6612
10k
V3P3D 10k EEPROM SCLK DI DO CS
DIO4 DIO5 DIOn
Figure 33: 3-Wire EEPROM Connection
3.9
UART0 (TX/RX)
The RX pin should be pulled down by a 10 k resistor and additionally protected by a 100 pF ceramic capacitor, as shown in Figure 34. 78M6612 RX 100pF 10k RX
TX
TX
Figure 34: Connections for the RX Pin 70 Rev. 1.2
DS_6612_001
78M6612 Data Sheet
3.10 UART1 Interface
The pins TX1 and RX1 can be used for a regular serial interface, e.g. by connecting a RS_232 transceiver, or they can be used to directly operate optical components, e.g. an infrared diode and phototransistor implementing a FLAG interface. Figure 35 shows the basic connections. The TX1 pin becomes active when the I/O RAM register TX1DIS is set to 0. The polarity of the TX1 and RX1 pins can be inverted with configuration bits TX1INV and RX1INV, respectively. The TX1 output may be modulated at 38 kHz when system power is present. Modulation is not available in BROWNOUT mode. The TX1MOD bit enables modulation. The duty cycle is controlled by OPT_FDC[1:0], which can select 50%, 25%, 12.5%, and 6.25% duty cycle. A 6.25% duty cycle means TX1 is low for 6.25% of the period. The receive pin (RX1) may need an analog filter when receiving modulated optical signals. With modulation, an optical emitter can be operated at higher current than nominal, enabling it to increase the distance along the optical path.
If operation in BROWNOUT mode is desired, the external components should be connected to V3P3D.
V3P3SY S 78M6612 RX 1 100pF 10k Phototransisto r V3P3SY S
R1
R2
TX1
LED
Figure 35: Connection for Optical Components
3.11 Connecting V1 and Reset Pins
A voltage divider should be used to establish that V1 is in a safe range when the power and measurement unit is in mission mode (V1 must be lower than 2.9 V in all cases in order to keep the hardware watchdog timer enabled). For proper debugging or loading code into the 78M6612 mounted on a PCB, it is necessary to have a provision like the header shown above R1 in Figure 36. A shorting jumper on this header pulls V1 up to V3P3 disabling the hardware watchdog timer. The parallel impedance of R1 and R2 should be approximately 8 to 10 k in order to provide hysteresis for the power fault monitor.
Rev. 1.2
71
78M6612 Data Sheet
DS_6612_001
R1 V3P3
R3 5k R2 C1 100pF V1
GND
Figure 36: Voltage Divider for V1 Even though a functional power and measurement unit will not necessarily need a reset switch, it is useful to have a reset pushbutton switch for prototyping, as shown in Figure 37, left side. The RESET signal may be sourced from V3P3SYS (functional in MISSION mode only), V3P3D (MISSION and BROWNOUT modes), VBAT (all modes, if battery is present), or from a combination of these sources, depending on the application. For a production unit, the RESET pin should be protected by the external components shown in Figure 37, right side. R 1 should be in the range of 100 and mounted as closely as possible to the IC. The RESET pin can also be directly connected to ground. Since the 78M6612 generates its own power-on reset, a reset button or circuitry, as shown in Figure 37, left side, is only required for test units and prototypes.
VBAT/ V3P3 D
R2 1k Reset Switch
V3P3 D
78M6612
78M6612
RESET RESET 10k R1 DGND 100 R1 DGND
1nF
Figure 37: External Components for RESET: Development Circuit (Left), Production Circuit (Right)
3.12 Connecting the Emulator Port Pins
Capacitors to ground must be used for protection from EMI. Production boards should have the ICE_E pin connected to ground. If the ICE pins are used to drive LCD segments, the pull-up resistors should be omitted, as shown in Figure 38, and 22 pF capacitors to GNDD should be used for protection from EMI. It is important to bring out the ICE_E pin to the programming interface in order to create a way for reprogramming parts that have the Flash SECURE bit (SFR 0xB2[6]) set. Providing access to ICE_E ensures that the part can be reset between erase and program cycles, which will enable programming devices to reprogram the part. The reset required is implemented with a watchdog timer reset (i.e. the hardware WDT must be enabled).
72
Rev. 1.2
DS_6612_001
LCD Segments (optional)
78M6612 Data Sheet
V3P3D 62 62
78M6612 ICE_E E_RST E_RXTX E_TCLK
62
22pF 22pF 22pF
Figure 38: External Components for the Emulator Interface
3.13 Crystal Oscillator
The oscillator of the 78M6612 drives a standard 32.768 kHz watch crystal. The oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability. The oscillator power dissipation is very low to maximize the lifetime of any battery backup device attached to VBAT. Board layouts with minimum capacitance from XIN to XOUT will require less battery current. Good layouts will have XIN and XOUT shielded from each other. Since the oscillator is self-biasing, an external resistor must not be connected across the crystal.
3.14 Flash Programming
Operational or test code can be programmed into the Flash memory using either an in-circuit emulator or the Flash Programmer Module (TFP-1) available from Teridian. The Flash programming procedure uses the E_RST, E_RXTX, and E_TCLK pins.
3.15 MPU Firmware Library
All application-specific MPU functions mentioned above under "Application Information" are available from Teridian as a standard ANSI C library and as ANSI "C" source code. The code is available as part of the Demonstration Kit for the 78M6612 IC. The Demonstration Kits come with the 78M6612 IC preprogrammed with demo firmware mounted on a functional sample PCB (Demo Board). The Demo Boards allow for quick and efficient evaluation of the IC without having to write firmware or having to supply an in-circuit emulator (ICE).
3.16 Measurement Calibration
Once the 78M6612 Power and Energy Measurement device has been installed in a measurement system, it is typically calibrated for tolerances of the current sensors, voltage dividers and signal conditioning components. The device can be calibrated using the gain and phase adjustment factors accessible to the CE. The gain adjustment is used to compensate for tolerances of components used for signal conditioning, especially the resistive components. Phase adjustment is provided to compensate for phase shifts introduced by certain types of current sensors. Due to the flexibility of the MPU firmware, any calibration method, such as calibration based on energy, or current and voltage can be implemented. It is also possible to implement segment-wise calibration (depending on current range). The 78M6612 supports common industry standard calibration techniques, such as single-point (energy-only), multi-point (energy, Vrms, Irms), and auto-calibration. Rev. 1.2 73
78M6612 Data Sheet
DS_6612_001
4 Firmware Interface
4.1 I/O RAM Map
`Not Used' bits are grayed out, contain no memory and are read by the MPU as zero. Reserved bits may be in use and should not be changed. This table lists only the SFR registers that are not generic 8051 SFR registers. Table 48: I/O RAM Map - In Numerical Order
Name Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Configuration: CE0 CE1 CE2 2000 2001 2002 EQU[2:0] PRE_SAMPS[1:0] MUX_DIV[1:0] PLL_OK PLS_INV Reserved CHOP_E[1:0] Not Used CKOUT_E[1:0] ECK_DIS FIR_LEN CE_E Reserved SUM_CYCLES[5:0] RTM_E Reserved VREF_DIS ADC_E MUX_ALT WD_OVF Reserved EX_RTC EX_XFR
COMP0 2003 Not Used CONFIG0 2004 VREF_CAL CONFIG1 2005 Reserved VERSION 2006 CONFIG2 2007 CE3 WAKE TMUX 20A8
Reserved COMP_STAT[0] MPU_DIV[2:0] FLSH66Z Reserved
VERSION[7:0] TX1E[1:0] Not Used Not Used SLEEP Not Used EX_PLL Not Used LCD_ONLY Not Used Not Used WAKE_RES EX_FWCOL Reserved CE_LCTN[4:0] WAKE_PRD[2:0] TMUX[4:0] OPT_FDC[1:0]
20A9 WAKE_ARM 20AA Not Used
Digital I/O: DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 DIO6 2008 2009 200A 200B DIO_EEX[1:0] Not Used Not Used Not Used RX1DIS DIO_R1[2:0] DIO_R3[2:0]* DIO_R5[2:0] DIO_R7[2:0] DIO_R9[2:0] DIO_R11[2:0] RX1INV DIO_PW Not Used Not Used Not Used Not Used Not Used Not Used DIO_PV
TX1MOD
TX1INV
Reserved (000) DIO_R2[2:0] DIO_R4[2:0] DIO_R6[2:0] DIO_R8[2:0] DIO_R10[2:0]
200C Not Used 200D Not Used 200E Not Used
Real Time Clock: RTC0 RTC1 RTC2 RTC3 RTC4 RTC5 RTC6 RTC7 WE 2015 2016 2017 2018 2019 201A 201B 201C 201F Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used RTC_SEC[5:0] RTC_MIN[5:0] RTC_HR[4:0] RTC_DAY[2:0] RTC_DATE[4:0] RTC_MO[3:0] RTC_YR[7:0]
RTC_DEC_SEC RTC_INC_SEC
Write enable for RTC
LCD Display Interface: LCDX LCDY LCDZ LCD0 2020 Not Used 2021 Not Used 2022 Not Used 2030 BME LCD_Y Not Used Reserved LCD_E Not Used LCD_NUM[4:0] LCD_MODE[2:0] Reserved LCD_SEG0[3:0] LCD_CLK[1:0]
Not Used
74
Rev. 1.2
DS_6612_001
... LCD19 LCD24 ... LCD38 ... 2043 2048 ... 2056 Not Used Not Used Not Used Not Used Not Used LCD_BLKMAP19[3:0]
78M6612 Data Sheet
... LCD_SEG19[3:0] LCD_SEG24[3:0] ... LCD_SEG38[3:0] LCD_BLKMAP18[3:0]
LCD_BLNK 205A RTM Probes: RTM0 RTM1 RTM2 RTM3 RTM0 RTM1 RTM2 RTM3
RTM0 RTM1 RTM2 RTM3
RTM0 RTM1 RTM2 RTM3
Pulse Generator: PLS_W PLS_ W PLS_I PLS_I PLS_W PLS_I PLS_W PLS_I
* = Only available on QFN-68 package. Reserved in the LQFP-64 package.
4.2
SFR Map (SFRs Specific to Teridian 80515)
`Not Used' bits are blacked out and contain no memory and are read by the MPU as zero. Reserved bits are in use and should not be changed. This table lists only the SFR registers that are not generic 8051 SFR registers.
Table 49: SFR Map - In Numerical Order
Name Digital I/O: DIO7 DIO8 DIO9 DIO10 DIO11 DIO12 80 A2 90 91 A0 A1 DIO_0[7:4] (Port 0) DIO_DIR0[7:4] DIO_1[7:6] DIO_DIR1[7:6] Not Used Not Used Not Used Not Used Reserved Reserved DIO_2[5] * DIO_DIR2 [5]* DIO_2[4:3] DIO_DIR2[4:3] DIO_0[3]* DIO_DIR0 [3]* DIO_0[2:1] DIO_DIR0[2:1] DIO_1[3:0] (Port 1) DIO_DIR1[3:0] Reserved Reserved DIO_2[1:0] (Port 2) DIO_DIR2[1:0] Reserved Reserved SFR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Interrupts and WD Timer: INTBITS IFLAGS Flash: ERASE FLSHCTL FPAG 94 B2 B7 PREBOOT SECURE Not Used FLSH_ERASE[7:0] Not Used Not Used Not Used
FLSH_MEEN
F8 E8
INT6
IE_PLLFALL IE_PLLRISE WD_RST
INT5 IE_WAKE
INT4
INT3
INT2
INT1 IE_RTC
INT0 IE_XFER
Reserved IE_FWCOL1 IE_FWCOL0
FLSH_PWE Not Used
FLSH_PGADR[6:0]
Serial EEPROM: EEDATA EECTRL 9E 9F EEDATA[7:0] EECTRL[7:0]
* = Only available on QFN-68 package. Reserved in the LQFP-64 package. Rev. 1.2 75
78M6612 Data Sheet
DS_6612_001
4.3
I/O RAM Description - Alphabetical Order
Bits with a W (write) direction are written by the MPU into configuration RAM. Typically, they are initially stored in Flash memory and copied to the configuration RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory space. The remaining bits are mapped to the address range 0x2xxx. Bits with R (read) direction can be read by the MPU. Columns labeled "Rst" and "Wk" describe the bit values upon reset and wake, respectively. No entry in one of these columns means the bit is either read-only or is powered by the non-volatile supply and is not initialized. Write-only bits will return zero when they are read. Table 50: I/O RAM Map - Alphabetical Order
Name ADC_E BME Location 2005[3] 2020[6] Rst 0 0 Wk 0 - Dir R/W R/W Description Enables ADC and VREF. When disabled, removes bias current. Battery Measure Enable. When set, a load current is immediately applied to the battery and it is connected to the ADC to be measured on Alternative Mux Cycles. See MUX_ALT bit. CE enable. CE program location. The starting address for the CE program is 1024*CE_LCTN. CE_LCTN must be defined before the CE is enabled. Chop enable for the reference bandgap circuit. The value of CHOP will change on the rising edge of MUXSYNC according to the value in CHOP_E: 1 00-toggle 01-positive 10-reversed 11-toggle 1 except at the mux sync edge at the end of SUMCYCLE. CKTEST Enable. The default is 00. 00-SEG19. 01-CK_FIR (5 MHz Mission, 32 kHz Brownout). 10-Not allowed (reserved for production test). 11-Same as 10. The status of the power fail comparator for V1. Connects dedicated I/O pins DIO2 through DIO11 as well as input pin DIO1 to internal resources. DIO_R3[2:0] is only available in the 68-pin package. If more than one input is connected to the same resource, the `MULTIPLE' column below specifies how they are combined. Resource Multiple NONE - Reserved OR T0 (Timer0 clock or gate) OR T1 (Timer1 clock or gate) OR High priority IO interrupt (int0 rising) OR Low priority IO interrupt (int1 rising) OR High priority IO interrupt (int0 110 OR falling) 111 Low priority IO interrupt (int1 falling) OR Programs the direction of pins DIO7- DIO1. DIO3 is only available on the 68-pin package. 1 indicates output. Ignored if the pin is not configured as I/O. See DIO_PV and DIO_PW for special option for DIO6 and DIO7 outputs. See DIO_EEX for special option for DIO4 and DIO5. DIO_Rx 000 001 010 011 100 101
CE_E CE_LCTN[4:0]
2000[4] 20A8[4:0]
0 31
0 31
R/W R/W
CHOP_E[1:0]
2002[5:4]
0
0
R/W
CKOUT_E[1:0]
2004[5,4]
00
00
R/W
COMP_STAT[0] DIO_R1[2:0] DIO_R2[2:0] DIO_R3[2:0]* DIO_R4[2:0] DIO_R5[2:0] DIO_R6[2:0] DIO_R7[2:0] DIO_R8[2:0] DIO_R9[2:0] DIO_R10[2:0] DIO_R11[2:0]
2003[0] 2009[6:4] 200A[2:0] 200A[6:4] 200B[2:0] 200B[6:4] 200C[2:0] 200C[6:4] 200D[2:0] 200D[6:4] 200E[2:0] 200E[6:4]
- 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0
R R/W
DIO_DIR0[7:1]*
SFRA2 [7:1]
0
0
R/W
76
Rev. 1.2
DS_6612_001
Name Location Rst 0 Wk 0 Dir R/W Description
78M6612 Data Sheet
DIO_DIR1[7:6, 3:0] SFR91 [7:6,3:0] DIO_DIR2[5:3,2:1] SFRA1 [5:3,2:1] SFR80 [7:1]
Programs the direction of pins DIO15-DIO14, DIO11-DIO8. 1 indicates output. Ignored if the pin is not configured as I/O. Programs the direction of pins DIO20- DIO19 and DIO17DIO16 (and DIO21 for the 68 QFN package). 1 indicates output. Ignored if the pin is not configured as I/O. The value on the pins DIO7-DIO1. DIO3 is only available on the 68-pin package. Pins configured as LCD will read zero. When written, changes data on pins configured as outputs. Pins configured as LCD or input will ignore write operations. The value on the pins DIO15-DIO14 and DIO11-DIO8. Pins configured as LCD will read zero. When written, changes data on pins configured as outputs. Pins configured as LCD or input will ignore write operations. The value on the pins DIO20-DIO19, and DIO17-DIO16 (and DIO21 for the 68 QFN package). Pins configured as LCD will read zero. When written, changes data on pins configured as outputs. Pins configured as LCD or input will ignore write operations. When set, converts DIO4 and DIO5 to interface with external EEPROM. DIO4 becomes SDCK and DIO5 becomes bi-directional SDATA. LCD_NUM must be less than or equal to 18. DIO_EEX[1:0] Function 00 Disable EEPROM interface 01 2-Wire EEPROM interface 10 3-Wire EEPROM interface 11 Not used Causes VARPULSE to be output on DIO7, if DIO7 is configured as output. LCD_NUM must be less than 15. Causes WPULSE to be output on DIO6, if DIO6 is configured as output. LCD_NUM must be less than 16. Serial EEPROM interface data. Serial EEPROM interface control. Emulator clock disable. When one, the emulator clock is disabled. This bit is to be used with caution! Inadvertently setting this bit will inhibit access to the part with the ICE interface and thus preclude Flash erase and programming operations. If ECK_ENA is set, it should be done at least 1000 ms after power-up to give emulators and programming devices enough time to complete an erase operation. Specifies the power equation to be used by the CE. Interrupt enable bits. These bits enable the XFER_BUSY, the RTC_1SEC, the FirmWareCollision, and PLL interrupts. Note that if one of these interrupts is to be enabled, its corresponding EX enable bit must also be set. See the Interrupts section for details. The length of the ADC decimation FIR filter. 1-384 cycles, 0-288 cycles When FIR_LEN=1, the ADC has 2.370370x higher gain.
0
0
R/W
DIO_0[7:1]*
0
0
R/W
DIO_1[7:6,3:0]
SFR90 [7:6,3:0]
0
0
R/W
DIO_2[5:3,1:0]
SFRA0 [5:3,1:0]
0
0
R/W
DIO_EEX[1:0]
2008[7:6]
0
0
R/W
DIO_PV DIO_PW EEDATA[7:0] EECTRL[7:0] ECK_DIS
2008[2] 2008[3] SFR9E SFR9F 2005[5]
0 0 0 30 0
0 0 0 30 0
R/W R/W R/W R/W R/W
EQU[2:0] EX_XFR EX_RTC EX_FWCOL EX_PLL FIR_LEN
2000[7:5] 2002[0] 2002[1] 2007[4] 2007[5] 2005[4]
0 0 0 0 0 0
0 0 0 0 0 0
R/W R/W
R/W
Rev. 1.2
77
78M6612 Data Sheet
Name FLSH_ERASE[7:0] Location SFR94[7:0] Rst 0 Wk 0 Dir W Description
DS_6612_001
Flash Erase Initiate FLSH_ERASE is used to initiate either the Flash Mass Erase cycle or the Flash Page Erase cycle. Specific patterns are expected for FLSH_ERASE in order to initiate the appropriate Erase cycle. (default = 0x00). 0x55 - Initiate Flash Page Erase cycle. Must be proceeded by a write to FLSH_PGADR @ SFR 0xB7. 0xAA - Initiate Flash Mass Erase cycle. Must be proceeded by a write to FLSH_MEEN @ SFR 0xB2 and the debug (CC) port must be enabled. Any other pattern written to FLSH_ERASE will have no effect.
FLSH_MEEN
SFRB2[1]
0
0
W
Mass Erase Enable 0 - Mass Erase disabled (default). 1 - Mass Erase enabled. Must be re-written for each new Mass Erase cycle. Flash Page Erase Address FLSH_PGADR[6:0] - Flash Page Address (page 0 thru 127) that will be erased during the Page Erase cycle. (default = 0x00). Must be re-written for each new Page Erase cycle. Program Write Enable 0 - MOVX commands refer to XRAM Space, normal operation (default). 1 - MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR. This bit is automatically reset after each byte written to Flash. Writes to this bit are inhibited when interrupts are enabled. Permits the values written by MPU to temporarily override the values in the fuse register (reserved for production test). Interrupt flags for Firmware Collision Interrupt. See Flash Memory Section for details. Indicates that the MPU was woken or interrupted (int 4) by System power becoming available, or more precisely, by PLL_OK rising. Firmware must write a zero to this bit to clear it. Indicates that the MPU has entered BROWNOUT mode because System power has become unavailable (int 4), or more precisely, because PLL_OK fell. Note: this bit will not be set if the part wakes into BROWNOUT mode because of the WAKE timer. Firmware must write a zero to this bit to clear it.
FLSH_PGADR[6:0] (FPAG)
SFRB7[7:1]
0
0
W
FLSH_PWE
SFRB2[0]
0
0
R/W
FOVRIDE
20FD[4]
0
0
R/W
IE_FWCOL0 IE_FWCOL1 IE_PLLRISE
SFRE8[2] SFRE8[3] SFRE8[6]
0 0 0
0 0 0
R/W R/W R/W
IE_PLLFALL
SFRE8[7]
0
0
R/W
IE_XFER IE_RTC
SFRE8[0] SFRE8[1]
0 0
0 0
R/W
Interrupt flags. These flags monitor the XFER_BUSY interrupt and the RTC_1SEC interrupt. The flags are set by hardware and must be cleared by the interrupt handler. Note that IE6, the interrupt 6 flag bit in the MPU must also be cleared when either of these interrupts occur. Indicates that the MPU was woken by the autowake timer. This bit is typically read by the MPU on bootup. Firmware must write a zero to this bit to clear it.
IE_WAKE
SFRE8[5]
0
-
R/W
78
Rev. 1.2
DS_6612_001
Name INTBITS Location SFRF8[6:0] Rst - Wk - Dir R/W Description
78M6612 Data Sheet
Interrupt inputs. The MPU may read these bits to see the input to external interrupts INT0, INT1, up to INT6. These bits do not have any memory and are primarily intended for debug use. Identifies which segments connected to SEG18 and SEG19 should blink. 1 means `blink.' Most significant bit corresponds to COM3. Least significant, to COM0. Sets the LCD clock frequency (for COM/SEG pins, not frame rate).
LCD_BLKMAP19[3:0] LCD_BLKMAP18[3:0] LCD_CLK[1:0]
205A[7:4] 205A[3:0] 2021[1:0]
0
-
R/W
0
-
R/W
Note: f w = 32768 Hz 00: f w /29, 01: f w/ 28, 10: f w /27, 11: f w /26
LCD_E LCD_MODE[2:0] 2021[5] 2021[4:2] 0 0 - - R/W R/W Enables the LCD display. When disabled, VLC2, VLC1, and VLC0 are ground as are the COM and SEG outputs. The LCD bias mode. 000: 4 states, bias 001: 3 states, bias 010: 2 states, 1/2 bias 011: 3 states, 1/2 bias 100: static display Number of dual-purpose LCD/DIO pins to be configured as LCD. This will be a number between 0 and 18. The first dual-purpose pin to be allocated as LCD is SEG41/DIO21 (SEG40/DIO20 on the 64 LQFP package). Thus if LCD_NUM=2, SEG41 and SEG 40 will be configured as LCD. The remaining SEG39 to SEG24 will be configured as DIO19 to DIO4. DIO1 and DIO2 (plus DIO3 on the QFN-68 package) are always available, if not used for UART1. See tables in Application Section. LCD_ONLY 20A9[5] 0 0 W Takes the 78M6612 to LCD mode. Ignored if system power is present. The part will awaken when autowake timer times out or when system power returns. LCD Segment Data. Each word contains information for from 1 to 4 time divisions of each segment. In each word, bit 0 corresponds to COM0, on up to bit 3 for COM3. These bits are preserved in LCD and SLEEP modes, even if their pin is not configured as SEG. In this case, they can be useful as general-purpose non-volatile storage. LCD Blink Frequency (ignored if blink is disabled or if segment is off). 0: 1 Hz (500 ms ON, 500 ms OFF) 1: 0.5 Hz (1s ON, 1s OFF) The MPU clock divider (from 4.9152 MHz). These bits may be programmed by the MPU without risk of losing control. 000-4.9152 MHz, 001-4.9152 MHz /2 , ..., 111-4.9152 7 MHz /2 MPU_DIV remains unchanged when the part enters BROWNOUT mode. MUX_ALT 2005[2] 0 0 R/W The MPU asserts this bit when it wishes the MUX to perform ADC conversions on an alternate set of inputs.
1
LCD_NUM[4:0]
2020[4:0]
0
-
R/W
LCD_SEG0[3:0] ... LCD_SEG19[3:0] LCD_SEG24[3:0] ... LCD_SEG38[3:0] LCD_Y
2030[3:0] ... 2043[3:0] 2048[3:0] ... 2056[3:0] 2021[6]
0 ... 0 0 ... 0 0
- ... - - ... - 0
R/W
R/W
R/W
MPU_DIV[2:0]
2004[2:0]
0
0
R/W
Rev. 1.2
79
78M6612 Data Sheet
Name MUX_DIV[1:0] Location 2002[7:6] Rst 0 Wk 0 Dir R/W Description
DS_6612_001
The number of states in the input multiplexer. 00 - Illegal 01 - 4 states 10 - 3 states 11 - 2 states Selects TX1 modulation duty cycle. OPT_FDC Function 00 50% Low 01 25% Low 10 12.5% Low 11 6.25% Low RX1 can be configured as an analog input to the UART1 comparator or as a digital input/output, DIO1. 0--RX1, 1--DIO1. Inverts result from RX1 comparator when 1. Affects only the UART1 input. Has no effect when RX1 is used as a DIO input. Configures the TX1 output pin. 00--TX1, 01--DIO2, 10--WPULSE, 11--VARPULSE Invert TX1 when 1. This inversion occurs before modulation. Enables modulation of TX1. When TX1MOD is set, TX1 is modulated when it would otherwise have been zero. The modulation is applied after any inversion caused by TX1INV. Indicates that system power is present and the clock generation PLL is settled. Determines the maximum width of the pulse (low going pulse). Maximum pulse width is (2*PLS_MAXWIDTH + 1)*TI . Where TI is PLS_INTERVAL. If PLS_INTERVAL=0, TI is the sample time (397s). If 255, disable MAXWIDTH. If the FIFO is used, PLS_INTERVAL must be set to 81. If PLS_INTERVAL = 0, the FIFO is not used and pulses are output as soon as the CE issues them. Inverts the polarity of WPULSE and VARPULSE. Normally, these pulses are active low. When inverted, they become active high. Indicates that preboot sequence is active. The duration of the pre-summer, in samples. 00-42, 01-50, 10-84, 11-100. The RTC interface. These are the `year', `month', `day', `hour', `minute' and `second' parameters of the RTC. The RTC is set by writing to these registers. Year 00 and all others divisible by 4 are defined as leap years. SEC 00 to 59 MIN 00 to 59 HR 00 to 23 (00=Midnight) DAY 01 to 07 (01=Sunday) DATE 01 to 31 MO 01 to 12 YR 00 to 99 Each write to one of these registers must be preceded by a write to 201F (WE).
OPT_FDC[1:0]
2007[1:0]
0
0
R/W
RX1DIS
2008[5]
0
0
R/W
RX1INV
2008[4]
0
0
R/W
TX1E[1,0] TX1INV TX1MOD
2007[7,6] 2008[0] 2008[1]
00 0 0
00 0 0
R/W R/W R/W
PLL_OK PLS_MAXWI DTH [7:0]
2003[6] 2080[7:0]
0 FF
0 FF
R R/W
PLS_INTERVAL [7:0] PLS_INV
2081[7:0]
0
0
R/W
2004[6]
0
0
R/W
PREBOOT PRE_SAMPS[1:0] RTC_SEC[5:0] RTC_MIN[5:0] RTC_HR[4:0] RTC_DAY[2:0] RTC_DATE[4:0] RTC_MO[3:0] RTC_YR[7:0]
SFRB2[7] 2001[7:6] 2015 2016 2017 2018 2019 201A 201B
- 0 - - - - - - -
- 0 - - - - - - -
R R/W R/W R/W R/W R/W R/W R/W R/W
80
Rev. 1.2
DS_6612_001
Name RTC_DEC_SEC RTC_INC_SEC Location 201C[1] 201C[0] Rst 0 0 Wk 0 0 Dir W Description
78M6612 Data Sheet
RTC time correction bits. Only one bit may be pulsed at a time. When pulsed, causes the RTC time value to be incremented (or decremented) by an additional second the next time the RTC_SEC register is clocked. The pulse width may be any value. If an additional correction is desired, the MPU must wait 2 seconds before pulsing one of the bits again. Each write to one of these bits must be preceded by a write to 201F (WE). Real Time Monitor enable. When `0', the RTM output is low. This bit enables the 2 wire version of RTM Four RTM probes. Before each CE code pass, the values of these registers are serially output on the RTM pin. The RTM registers are ignored when RTM_E=0. Enables security provisions that prevent external reading of Flash memory and CE program RAM. This bit is reset on chip reset and may only be set. Attempts to write zero are ignored. Takes the 78M6612 to sleep mode. Ignored if system power is present. The part will wake when the autowake timer times out or when system power returns. The number of pre-summer outputs summed in the final summer. Selects one of 32 signals for TMUXOUT. [4:0] 0x00 0x02 0x04 0x06 0x08 0x0A Selected Signal DGND (analog) Reserved Reserved VBIAS (analog) Reserved Reserved [4:0] 0x01 0x03 0x05 0x07 0x09 0x0 B0x13 0x15 0x18 Selected Signal Reserved Reserved Reserved Not used Reserved Reserved
RTM_E RTM0[7:0] RTM1[7:0] RTM2[7:0] RTM3[7:0] SECURE
2002[3] 2060 2061 2062 2063 SFRB2[6]
0 0 0 0 0 0
0 0 0 0 0 -
R/W R/W
R/W
SLEEP
20A9[6]
0
0
W
SUM_CYCLES[5:0] TMUX[4:0]
2001[5:0] 20AA[4:0]
0 2
0 -
R/W R/W
0x14 0x16 - 0x17 0x19 0x1B 0x1D 0x1F VERSION[7:0] 2006[7:0] - - R
RTM (Real time output from CE) Not used
MUX_SYNC CK_MPU RTCLK_2P5 XFER_BUSY
0x1 A 0x1 C 0x1 E
WDTR_E, comparator 1 Output AND V1LT3) RXD, from optical interface, after optional inversion CK_10M Reserved CE_BUSY
VREF_CAL VREF_DIS
2004[7] 2004[3]
0 0
0 1
R/W R/W
The version index. This word may be read by firmware to determine the silicon version. VERSION[7:0] 0000 0110 Brings VREF to VREF pad. This feature is disabled when VREF_DIS=1. Disables the internal voltage reference.
Rev. 1.2
81
78M6612 Data Sheet
Name WAKE_ARM Location 20A9[7] Rst 0 Wk - Dir W Description
DS_6612_001
Arm the autowake timer. Writing a 1 to this bit arms the autowake timer and presets it with the values presently in WAKE_PRD and WAKE_RES. The autowake timer is reset and disarmed whenever the MPU is in MISSION mode or BROWNOUT mode. The timer must be armed at least three RTC cycles before the SLEEP or LCD-ONLY mode is commanded. Sleep time. Time=WAKE_PRD[2:0]*WAKE_RES. Default=001. Maximum value is 7. Resolution of WAKE timer: 1 - 1 minute, 0 - 2.5 seconds. WD timer bit: Possible operations to this bit are: Read: Gets the status of the flag IE_PLLFALL Write 0: Clears the flag. Write 1:.Resets the WDT. The WD overflow status bit. This bit is set when the WD timer overflows. It is powered by the non-volatile supply and at bootup will indicate if the part is recovering from a WD overflow or a power fault. This bit should be cleared by the MPU on bootup. It is also automatically cleared when RESET is high. Write operations on the RTC registers must be preceded by a write operation to WE.
WAKE_PRD WAKE_RES WD_RST
20A9[2:0] 20A9[3] SFRE8[7]
001 0 0
- - 0
R/W R/W W
WD_OVF
2002[2]
0
0
R/W
WE
201F[7:0]
-
-
W
82
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78M6612 Data Sheet
4.4
CE Interface Description
4.4.1 CE Program
The CE program is supplied by Teridian as a data image that can be merged with the MPU operational code for measurement applications. Typically, the CE program covers most applications and does not need to be modified. Other variations of CE code may be available from Teridian. The description in this section applies to CE code revision CE6612_OMU_S2_A01_V1_2.
4.4.2 Formats
All CE words are 4 bytes. Unless specified otherwise, they are in 32-bit two's complement (-1 = 0xFFFFFFFF). `Calibration' parameters are defined in Flash memory (or external EEPROM) and must be copied to CE data memory by the MPU before enabling the CE. `Internal' variables are used in internal CE calculations. `Input' variables allow the MPU to control the behavior of the CE code. `Output' variables are outputs of the CE calculations. The corresponding MPU address for the most significant byte is given by 0x1000 + 4 x CE_address and 0x1003 + 4 x CE_address for the least significant byte.
4.4.3 Constants
Constants used in the CE Data Memory tables are: F S = 32768 Hz/13 = 2520.62 Hz. F 0 is the fundamental frequency. IMAX is the external rms current corresponding to 250 mV pk at the inputs IA and IB. VMAX is the external rms voltage corresponding to 250 mV pk at the VA and VB inputs. NACC, the accumulation count for energy measurements is PRE_SAMPS * SUM_CYCLES. Accumulation count time for energy measurements is PRE_SAMPS * SUM_CYCLES/F S .
The system constants IMAX and VMAX are used by the MPU to convert internal quantities (as used by the CE) to external, i.e. measurement quantities. Their values are determined by the off-chip scaling of the voltage and current sensors used in an actual measurement unit. The LSB values used in this document relate digital quantities at the CE or MPU interface to external measurement input quantities. For example, if a SAG threshold of 80V peak is desired at the measurement input, the digital value that should be programmed into SAG_THR would be 80V/SAG_THRLSB, where SAG_THRLSB is the LSB value in the description of SAG_THR. The parameters EQU, CE_E, PRE_SAMPS, and SUM_CYCLES essential to the function of the CE are stored in I/O RAM (see the I/O RAM section).
4.4.4 Environment
Before starting the CE using the CE_E bit, the MPU has to establish the proper environment for the CE by implementing the following steps: Load the CE data into CE DRAM. Establish the equation to be applied in EQU. Establish the accumulation period and number of samples in PRE_SAMPS and SUM_CYCLES. Establish the number of cycles per ADC mux frame. Set PLS_INTERVAL[7:0] = 81. Set FIR_LEN = 1 and MUX_DIV[1:0] = 01.
There must be thirteen 32768 Hz cycles per ADC mux frame (see System Timing Diagram, Figure 16). This means that the product of the number of cycles per frame and the number of conversions per frame Rev. 1.2 83
78M6612 Data Sheet
DS_6612_001
must be 12 (allowing for one settling cycle). The required configuration is FIR_LEN = 1 (three cycles per conversion) and MUX_DIV[1:0] = 01 (4 conversions per mux frame). During operation, the MPU is in charge of controlling the multiplexer cycles, for example by inserting an alternate multiplexer sequence at regular intervals using MUX_ALT. This enables temperature measurement. The polarity of chopping circuitry must be altered for each sample. It must also alternate for each alternate multiplexer reading. This is accomplished by maintaining CHOP_E = 00.
4.4.5 CE Calculations
The CE performs the precision computations necessary to accurately measure energy. These computations include offset cancellation, products, product smoothing, product summation, frequency detection, VAR calculation, sag detection, peak detection, and voltage phase measurement. Refer to the applicable 78M6612 Firmware Description Document.
4.4.6 CE Status
Since the CE_BUSY interrupt occurs at 2520.6 Hz, it is desirable to minimize the computation required in the interrupt handler of the MPU. The MPU can read the CE status word at every CE_BUSY interrupt. CE Address 0x70 Name CESTATUS Description See description of CE status word below.
The CE Status Word is used for generating early warnings to the MPU. It contains sag warnings for VA as well as F0, the derived clock operating at the fundamental input frequency. CESTATUS provides information about the status of voltage and input AC signal frequency, which are useful for generating early power fail warnings, e.g. to initiate necessary data storage. CESTATUS represents the status flags for the preceding CE code pass (CE busy interrupt). Sag alarms are not remembered from one code pass to the next. The CE Status word is refreshed at every CE_BUSY interrupt. The significance of the bits in CESTATUS is shown in the table below: CESTATUS [bit] 31-29 28 27 26 25 24-0 Name Not Used F0 Reserved SAG_B SAG_A Not Used Normally zero. Becomes one when VB remains below SAG_THR for SAG_CNT samples. Will not return to zero until VB rises above SAG_THR. Normally zero. Becomes one when VA remains below SAG_THR for SAG_CNT samples. Will not return to zero until VA rises above SAG_THR. These unused bits will always be zero. Description These unused bits will always be zero. F0 is a square wave at the exact fundamental input frequency.
84
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78M6612 Data Sheet
The CE is initialized by the MPU using CECONFIG (CESTATE.). This register contains in packed form SAG_CNT, FREQSEL, EXT_PULSE, I1_SHUNT, I2_SHUNT, PULSE_SLOW, and PULSE_FAST. CE Address 0x0E Name CECONFIG Default 0x5001 Description See description of CECONFIG below.
The significance of the bits in CECONFIG is shown in the table below. The CE controls the pulse rate based on W1SUM_X + W2SUM_X (and VAR1SUM_X + VAR2SUM_X). Note: The 78M6612 Demo Code creep function halts pulse generation. CECONFIG [bit] [15:8] [7] [6] [5] [4] Name Default 80 (0x50) 0 0 0 0 Description Number of consecutive voltage samples below SAG_THR before a sag alarm is declared. The maximum value is 255. SAG_THR is at address 0x14. Unused Unused Unused Selects outlet to be used for pulse generation. PULSESEL 0=A 1=B Current sensor selection. [3:2] SENSORSEL 11 00 = CT 11 = Shunt When PULSE_SLOW = 1, the pulse generator input is reduced by a factor of 64. When PULSE_FAST = 1, the pulse generator input is increased 16x. These two parameters control the pulse gain factor X (see table below). Allowed values are 1 or 0. Default is 01 (X = 6/64). X 1.5 * 2 = 6
[0] PULSE_SLOW 0
2
SAG_CNT - - -
[1]
PULSE_FAST
0
PULSE_FAST 0 0 1 1
PULSE_SLOW 0 1 0 1
1.5 * 2-4 = 0.09375 1.5 * 2 = 96 1.5
6
4.4.7 CE Transfer Variables
When the MPU receives the XFER_BUSY interrupt, it knows that fresh data is available in the transfer variables. The transfer variables can be categorized as: 1. Fundamental energy measurement variables 2. Instantaneous (RMS) values 3. Other measurement parameters 4. Pulse generation variables 5. Current shunt variables 6. Calibration parameters Rev. 1.2
85
78M6612 Data Sheet 4.4.7.1 Fundamental Energy Measurement Variables
DS_6612_001
The table below describes each transfer variable for fundamental energy measurement. All variables are signed 32 bit integers. Accumulated variables such as WSUM are internally scaled so they have at least 2x margin before overflow when the integration time is 1 second. Additionally, the hardware will not permit output values to `fold back' upon overflow. CE Address 0x74 0x75 0x76 0x77 Name W1SUM_X W2SUM_X VAR1SUM_X VAR2SUM_X Description The sum of Watt samples from each measurement element (In_8 is the gain configured by IA_SHUNT or IB_SHUNT). LSB = 1.67380 *10-13 VMAX * IMAX / In_8 Wh. The sum of VAR samples from each measurement element (In_8 is the gain configured by IA_SHUNT or IB_SHUNT). LSB = 1.67380 *10-13 VMAX * IMAX / In_8 Wh.
WxSUM_X is the Wh value accumulated for element `X' in the last accumulation interval and can be computed based on the specified LSB value. For example with VMAX = 600V and IMAX = 52A, LSB (for WxSUM_X) is 0.005222 Wh. 4.4.7.2 Instantaneous Energy Measurement Variables The Frequency measurement is computed using the Frequency locked loop for the selected phase. IxSQSUM_X and VxSQSUM are the squared current and voltage samples acquired during the last accumulation interval. INSQSUM_X can be used for computing the neutral current. CE Address 0x72 0x78 0x79 0x7A 0x7B 0x7C 0x18 Name FREQ_X I1SQSUM_X I2SQSUM_X V1SQSUM_X V2SQSUM_X V3SQSUM_X WSUM_ACCUM Description Fundamental frequency. LSB
FS 0.587 10 -6 Hz 2 32
The sum of squared current samples from each element. LSB = 4.1845*10-14 IMAX2 A2h The sum of squared voltage samples from each element. LSB= 6.6952 * 10-13 VMAX2 V2h The sum of squared voltage difference samples (V1-V2) between the elements. LSB= 6.6952 * 10-13 VMAX2 V2h This is the roll-over accumulator for WPULSE.
The RMS values can be computed by the MPU from the squared current and voltage samples as follows:
Ix RMS =
IxSQSUM LSB 3600 FS N ACC
VxRMS =
VxSQSUM LSB 3600 FS N ACC
86
Rev. 1.2
DS_6612_001 4.4.7.3 Other Measurement Parameters
78M6612 Data Sheet
MAINEDGE_X is useful for implementing a real-time clock based on the input AC signal. MAINEDGE_X is the number of half-cycles accounted for in the last accumulated interval for the AC signal. TEMP_RAW may be used by the MPU to monitor chip temperature or to implement temperature compensation. CE Address 0x73 0x71 0x19 Name Default Description The number of zero crossings of the selected voltage in the previous accumulation interval. Zero crossings are either direction and are debounced. Filtered, unscaled reading from the temperature sensor. Scales all voltage and current inputs. 16384 provides unity gain. The threshold for sag warnings. The default value is equivalent to 80V RMS if VMAX = 600V. The LSB value is VMAX * 4.255*10-7V (peak).
MAINEDGE_X TEMP_RAW_X GAIN_ADJ
N/A N/A 16384
0x11
SAG_THR
313000
GAIN_ADJ is a scaling factor for measurements based on the temperature. GAIN_ADJ is controlled by the MPU for temperature compensation. 4.4.7.4 Pulse Generation CE Address Name Default Description Kh = VMAX *IMAX * 47.1132 / (WRATE * N ACC * X) Wh/pulse. The default value results in a Kh of 3.2 Wh/pulse when 2520 samples are taken in each accumulation interval (and VMAX=600, IMAX = 52, X = 6). The maximum value for WRATE is 215 - 1. WRATE controls the number of pulses that are generated per measured Wh and VARh quantities. The lower WRATE is the slower the pulse rate for measured energy quantity. The measurement constant Kh is derived from WRATE as the amount of energy measured for each pulse. That is, if Kh = 1Wh/pulse, a power applied to the measurement unit of 120 V and 30 A results in one pulse per second. If the load is 240 V at 150 A, ten pulses per second will be generated. The maximum pulse rate is 7.5 kHz. The maximum time jitter is 67 s and is independent of the number of pulses measured. Thus, if the pulse generator is monitored for 1 second, the peak jitter is 67 ppm. After 10 seconds, the peak jitter is 6.7 ppm. The average jitter is always zero. If it is attempted to drive either pulse generator faster than its maximum rate, it will simply output at its maximum rate without exhibiting any rollover characteristics. The actual pulse rate, using WSUM as an example, is:
0x0F
WRATE
486
RATE =
WRATE WSUM FS X Hz , 2 46
where F S = sampling frequency (2520.6 Hz), X = Pulse speed factor. Rev. 1.2 87
78M6612 Data Sheet 4.4.7.5 CE Calibration Parameters
DS_6612_001
The table below lists the parameters that are typically entered to effect calibration of measurement accuracy. CE Address 0x08 0x09 0x0A 0x0B Name CAL_IA CAL_IB CAL_VA CAL_VB Default 16384 16384 16384 16384 Description These constants control the gain of their respective channels. The nominal value for each parameters is 214 = 16384. The gain of each channel is directly proportional to its CAL parameter. Thus, if the gain of a channel is 1% slow, CAL should be scaled by 1/(1 - 0.01). These two constants control the CT phase compensation. No compensation occurs when PHADJ_X = 0. As PHADJ_X is increased, more compensation (lag) is introduced. Range: 215 - 1. If it is desired to delay the current by the angle :
0x0C
PHADJ_A
0
PHADJ _ X = 2 20
0x0D PHADJ_B 0
PHADJ _ X = 2 20
0.02229 TAN at 60 Hz 0.1487 - 0.0131 TAN
0.0155 TAN at 50 Hz 0.1241 - 0.009695 TAN
4.4.7.6 Other CE Parameters The table below shows CE parameters used for suppression of noise due to scaling and truncation effects. CE Address 0x12 Name Default Description This parameter is added to the Watt calculation for element 1 to compensate for input noise and truncation. LSB = VMAX * IMAX * 1.8541*10-10 W This parameter is added to the Watt calculation for element 2 to compensate for input noise and truncation. Same LSB as QUANTA. This parameter is added to the VAR calculation for element 1 to compensate for input noise and truncation. LSB = VMAX * IMAX * 1.8541*10-10 W This parameter is added to the VAR calculation for element 2 to compensate for input noise and truncation. Same LSB as for QUANT_VARA. This parameter is added to compensate for input noise and truncation in the squaring calculations for I2. QUANT_IA affects only I1SQSUM. LSB = IMAX2 * 4.6351 * 10-11 A2 This parameter is added to compensate for input noise and truncation in the squaring calculations for I2. QUANT_IB affects only I2SQSUM. Same LSB as for QUANT_IA.
QUANTA
0
0x13
QUANTB
0
0x14
QUANT_VARA
0
0x15
QUANT_VARB
0
0x16
QUANT_IA
0
0x17
QUANT_IB
0
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78M6612 Data Sheet
5 Electrical Specifications
5.1 Absolute Maximum Ratings
-0.5 V to 4.6 V -0.5 V to 4.6 V -0.5 V to +0.5 V -10 mA to 10 mA, -0.5 V to 4.6 V -10 mA to +10 mA, -0.5 V to V3P3A+0.5 V -10 mA to +10 mA, -0.5 V to 3.0 V -10 mA to +10 mA -0.5 V to V3P3A+0.5 V -10 mA to +10 mA -0.5 V to 3.0 V -1 mA to +1 mA, -0.5 to V3P3D+0.5 -10 mA to +10 mA, -0.5 to 6 V -15mA to +15mA, -0.5V to V3P3D+0.5V -0.5V to V3P3D+0.5V 140 C 125 C -45 C to +165 C 250 C 4 kV Supplies and Ground Pins: V3P3SYS, V3P3A VBAT GNDD Analog Output Pins: V3P3D
VREF V2P5 Analog Input Pins: IA, VA, IB, VB, V1 XIN, XOUT All Other Pins: Configured as SEG or COM drivers Configured as Digital Inputs Configured as Digital Outputs All other pins Operating junction temperature (peak, 100 ms) Operating junction temperature (continuous) Storage temperature Solder temperature - 10 second duration ESD stress on all pins
Stresses beyond Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GNDA.
Rev. 1.2
89
78M6612 Data Sheet
DS_6612_001
5.2
Recommended External Components
Name C1 C2 CSYS C2P5 XTAL CXS CXL
From V3P3A V3P3D V3P3SYS V2P5 XIN XIN XOUT
To AGND DGND DGND DGND XOUT AGND AGND
Function Bypass capacitor for 3.3V supply Bypass capacitor for 3.3V output Bypass capacitor for V3P3SYS Bypass capacitor for V2P5 32.768 kHz crystal - electrically similar to ECS .327-12.5-17X or Vishay XT26T, load capacitance 12.5 pF Load capacitor for crystal (exact value depends on crystal specifications and parasitic capacitance of board).
Value 0.120% 0.120% 1.030% 0.120% 32.768 2710% 2710%
Unit F F F F kHz pF pF
Depending on trace capacitance, higher or lower values for CXS and CXL must be used. Capacitance from XIN to GNDD and XOUT to GNDD (combining pin, trace and crystal capacitance) should be 35 pF to 37 pF.
5.3
Recommended Operating Conditions
Condition Normal Operation Battery Backup Min 3.0 0 Typ 3.3 Max 3.6 3.6 Unit V V
Parameter 3.3V Supply Voltage (V3P3SYS, V3P3A) V3P3A and V3P3SYS must be at the same voltage
No Battery VBAT Battery Backup BRN and LCD modes SLEEP mode MISSION mode BROWNOUT mode LCD mode
Externally Connect to V3P3SYS 3.0 2.0 -40 3.8 3.8 +85 V3P3SYS+0.3 VBAT+0.3 VBAT+0.3 V V C V V V
Operating Temperature Maximum input voltage on DIO/SEG pins configured as DIO input. *
*Exceeding this limit will distort the LCD waveforms on other pins.
90
Rev. 1.2
DS_6612_001
78M6612 Data Sheet
5.4
Performance Specifications
5.4.1 Input Logic Levels
Parameter Digital high-level input voltage , V IH Digital low-level input voltage , V IL Input pull-up current, IIL E_RXTX, E_RST, CKTEST Other digital inputs Input pull down current, IIH ICE_E Other digital inputs

Condition
Min 2
Typ
Max 0.8
Unit V V A A A A A
VIN=0V, ICE_E=1 10 10 -1 VIN=V3P3D 10 -1 0 100 1 100 100 1
0
In battery powered modes, digital inputs should be below 0.3 V or above 2.5 V to minimize battery current.
5.4.2 Output Logic Levels
Parameter Condition I LOAD = 1 mA Digital high-level output voltage V OH I LOAD = 15 mA Digital low-level output voltage V OL TX1 VOH (V3P3D-TX1) TX1 VOL I LOAD = 1 mA I LOAD = 15 mA ISOURCE=1 mA ISINK=20 mA Min V3P3D -0.4 V3P3D -0.6 0 0.4 0.8 0.4 0.7 Typ Max Unit V V V V V V
5.4.3 Power-Fault Comparator
Parameter Offset Voltage V1-VBIAS Hysteresis Current V1 Response Time V1 WDT Disable Threshold (V1-V3P3A) Vin = VBIAS - 100 mV +100 mV overdrive Condition Min -20 0.8 2 -400 5 Typ Max +15 1.2 10 -10 Unit mV
A s
mV
5.4.4 Battery Monitor
BME=1
Parameter Load Resistor LSB Value - does not include the 9bit left shift at CE input. Offset Error Rev. 1.2
Condition FIR_LEN=0 FIR_LEN=1
Min 27 -6.0 -2.6 -200
Typ 45 -5.4 -2.3 -72
Max 63 -4.9 -2.0 +100
Unit k V V mV 91
78M6612 Data Sheet
DS_6612_001
5.4.5
92
Rev. 1.2
DS_6612_001
78M6612 Data Sheet
Supply Current
Parameter V3P3A + V3P3SYS current Condition Normal Operation, V3P3A=V3P3SYS=3.3V MPU_DIV[1:0]=3 (614 kHz) CKOUT_E[1:0]=00, CE_EN=1, RTM_E=0, ECK_DIS=1, ADC_E=1, ICE_E=0 Same conditions as above Normal Operation as above, except write Flash at maximum rate, CE_E=0, ADC_E=0 VBAT=3.6V BROWNOUT mode, <25C BROWNOUT mode, <>5C VBAT current LCD Mode, 25 C LCD mode, over temperature SLEEP Mode, 25 C Sleep mode, over temperature Min Typ 6.1 Max 7.7 Unit mA
VBAT current V3P3A + V3P3SYS current vs. MPU clock frequency V3P3A + V3P3SYS current, Write Flash
-300
+300
nA mA/ MHz
0.5
9.1
10
mA
48 65 5.7 2.9
120 150 8.5 15 5.0 10
A A A A A A
Current into V3P3A and V3P3SYS pins is not zero if voltage is applied at these pins in brownout, LCD or sleep modes.
5.4.6 V3P3D Switch
Parameter On resistance - V3P3SYS to V3P3D On resistance - VBAT to V3P3D Condition | I V3P3D | 1 mA | I V3P3D | 1 mA Min Typ Max 10 40 Unit
5.4.7 2.5V Voltage Regulator
Unless otherwise specified, load = 5 mA Parameter Voltage overhead V3P3-V2P5 PSSR V2P5/V3P3 Condition Reduce V3P3 until V2P5 drops 200 mV RESET=0, iload=0 -3 Min Typ Max 440 +3 Unit mV mV/V
5.4.8 Low Power Voltage Regulator
Unless otherwise specified, V3P3SYS=V3P3A=0 Parameter V2P5 V2P5 load regulation VBAT voltage requirement Condition ILOAD=0 ILOAD=0 mA to 1 mA ILOAD=1 mA, Reduce VBAT until REG_LP_OK=0 Min 2.0 Typ 2.5 Max 2.7 30 3.0 Unit V mV V
Rev. 1.2
93
78M6612 Data Sheet PSRR V2P5/VBAT ILOAD=0 -50
DS_6612_001 50 mV/V
94
Rev. 1.2
DS_6612_001
78M6612 Data Sheet
5.4.9 Crystal Oscillator
Parameter Maximum Output Power to Crystal XIN to XOUT Capacitance Capacitance to DGND XIN XOUT Condition Crystal connected Min Typ Max 1 3 5 5 Unit W pF pF pF
5.4.10 VREF, VBIAS
Unless otherwise specified, VREF_DIS=0 Parameter VREF output voltage, VNOM(25) VREF chop step VREF output impedance VNOM definitionA VREF temperature coefficients TC1 TC2 VREF aging VREF(T) deviation from VNOM(T) VREF (T ) - VNOM (T ) 10 6 VNOM 62 VBIAS voltage
A
Condition Ta = 22C VREF_CAL =1, ILOAD = 10 A, -10 A
Min 1.193
Typ 1.195
Max 1.197 50 2.5
Unit V mV k V V/C V/C2 ppm/ year
VNOM (T ) = VREF (22) + (T - 22)TC1 + (T - 22) 2 TC 2
+7.0 -0.341 25
Ta = -40C to +85C Ta = 25 C Ta = -40 C to 85 C
-40 (-1%) (-4%) 1.6 1.6
+40 (+1%) (+4%)
ppm/ C V V
This relationship describes the nominal behavior of VREF at different temperatures.
5.4.11 LCD Drivers
Applies to all COM and SEG pins. Parameter VLC2 Max Voltage VLC1 Voltage, bias 1/2 bias VLC0 Voltage, bias 1/2 bias Condition With respect to VLCD With respect to 2*VLC2/3 With respect to VLC2/2 With respect to VLC2/3 With respect to VLC2/2 Min -0.1 -4 -3 -3 -3 Typ Max 0+.1 0 +2 +2 +2 Unit V % % % %
VLCD is V3P3SYS in MISSION mode and VBAT in BROWNOUT and LCD modes.
5.4.12
Rev. 1.2
95
78M6612 Data Sheet
DS_6612_001
ADC Converter, V3P3A Referenced
FIR_LEN=0, VREF_DIS=0, LSB values do not include the 9-bit left shift at CE input. Parameter Recommended Input Range (Vin-V3P3A) Voltage to Current Crosstalk: Vin = 200 mV peak, 65 Hz, on VA -10 10 V/V Condition Min -250 Typ Max 250 Unit mV peak
10 6 *Vcrosstalk cos(Vin - Vcrosstalk ) Vcrosstalk = largest Vin measurement on IA or IB
THD (First 10 harmonics) 250 mV-pk 20 mV-pk Input Impedance Temperature coefficient of Input Impedance LSB size
Vin=65 Hz, 64 kpts FFT, BlackmanHarris window Vin=65 Hz Vin=65 Hz FIR_LEN=0 FIR_LEN=1 FIR_LEN=0 FIR_LEN=1 40 1.7 357 151 +884736 209715 2
-75 -90 90
dB dB k /C nV/LSB
Digital Full Scale ADC Gain Error vs %Power Supply Variation 10 6 Nout PK 357 nV / VIN 100 V 3P3 A / 3.3 Input Offset (Vin-V3P3A)
LSB
Vin=200 mV pk, 65 Hz V3P3A=3.0V, 3.6V -10
50
ppm/ % mV
10
5.4.13 UART1 Interface
Parameter TX1 VOH (V3P3D-TX1) TX1 VOL Condition ISOURCE=1 mA ISINK=20 mA Min Typ Max 0.4 0.7 Unit V V
5.4.14 Temperature Sensor
Parameter Nominal Sensitivity (S n ) Nominal (N n ) Temperature Error
( N (T ) - N n ) ERR = T - + Tn Sn

Condition TA=25C, TA=75C, FIR_LEN = 1 Nominal relationship: N(T)= S n *(T-T n )+N n TA = -40C to +85C Tn = 25C
Min
Typ -2180 1.0
Max
Unit LSB/C 106 LSB
-10
+10
C
LSB values do not include the 9-bit left shift at CE input. N n is measured at T n during calibration and is stored in MPU or CE for use in temperature calculations. Rev. 1.2
96
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78M6612 Data Sheet
5.5
Timing Specifications
5.5.1 RAM and Flash Memory
Parameter CE DRAM wait states Condition CKMPU = 4.9152 MHz CKMPU = 1.25 MHz CKMPU = 614 kHz Flash Read Pulse Width Flash write cycles Flash data retention Flash data retention Flash byte writes between page or mass erase operations V3P3A=V3P3SYS=0 BROWNOUT MODE -40 C to +85 C 25 C 85 C Min 5 2 1 30 20,000 100 10 2 100 Typ Max Unit Cycles Cycles Cycles ns Cycles Years Years Cycles
5.5.2 Flash Memory Timing
Parameter Write Time per Byte Page Erase (512 bytes) Mass Erase Condition Min Typ Max 42 20 200 Unit s ms ms
5.5.3 EEPROM Interface
Parameter Condition CKMPU=4.9152 MHz, Using interrupts CKMPU=4.9152 MHz, "bit-banging" DIO4/5 CKMPU=4.9152 MHz Min Typ 78 150 500 Max Unit kHz kHz kHz
Write Clock frequency (I C)
2
Write Clock frequency (3-wire)
5.5.4 RESET and V1
Parameter Reset pulse fall time Reset pulse width V1 Response Time +100 mv overdrive 5 10 37 100 Condition Min Typ Max 1 Unit s s s
5.5.5 RTC
Parameter Range for date Condition Min 2000 Typ Max 2255 Unit year
Rev. 1.2
97
78M6612 Data Sheet
DS_6612_001
5.5.6 Typical Performance Data
Wh Accuracy (%)
0.5 0.4 0.3 0.2 0.1
Accuracy (%)
0 -0.1 -0.2 -0.3 -0.4 -0.5 0.01 0.1 1 10
Wh Accuracy (%)
Current (A)
Figure 39: Wh Accuracy, 20 mA to 20 A at 120 V/60 Hz and Room Temperature Using a 4 m Current Shunt
2 1 0 -1
Error [%]
-2 -3 -4 -5 -6 -7 -8 1 3 5 7 9 11 13
Harmonic 50Hz Harmonic Data 60Hz Harmonic Data
15
17
19
21
23
25
Measured at current distortion amplitude of 40% and voltage distortion amplitude of 10%. Figure 40: Measurement Accuracy over Harmonics at 240 V, 30A per IEC62053-2x
98
Rev. 1.2
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Relative Accuracy over Temperature
40
78M6612 Data Sheet
Accuracy [PPM/C]
30 20 10 0 -10 -20 -30 -60 -40 -20 0 20 40 60 80 100 Temperature [C]
Figure 41: Typical Measurement Accuracy over Temperature Relative to 25C
Rev. 1.2
99
78M6612 Data Sheet
DS_6612_001
6 Packaging
6.1 64 LQFP Package
6.1.1 Pinout
E_TCLK/SEG33 E_RST/SEG32 GNDD XOUT TEST XIN GNDD RX1/DIO1 V1 VREF IA IB VB VA V3P3A GNDA
GNDD E_RXTX/SEG38 TX1/DIO2 TMUXOUT TX0 SEG3 V3P3D SEG19/CKTEST V3P3SYS SEG4 SEG5 SEG37/DIO17 COM0 COM1 COM2 COM3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
TERIDIAN 78M6612-IGT
RESET V2P5 VBAT RX SEG40/DIO20 SEG31/DIO11 SEG30/DIO10 SEG29/DIO9 SEG28/DIO8 SEG27/DIO7 SEG26/DIO6 SEG25/DIO5 SEG24/DIO4 ICE_E SEG18 SEG17
100
SEG0 SEG1 SEG2 SEG34/DIO14 SEG35/DIO15 SEG36/DIO16 SEG39/DIO19 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG16
Figure 42: 64-Pin LQFP Pinout
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Rev. 1.2
DS_6612_001
78M6612 Data Sheet
6.1.2
Package Outline (LQFP 64)
11.7 12.3
11.7 12.3
PIN No. 1 Indicator 9.8 10.2 0.00 0.20
+
0.50 Typ. 0.60 Typ.
0.14 0.28
1.40 1.60
NOTE: Controlling dimensions are in mm.
Rev. 1.2
101
78M6612 Data Sheet
DS_6612_001
6.1.3 Recommended PCB Land Pattern for the LQFP-64 Package
x
y
e
A
G
x
y
e A G
Recommended PCB Land Pattern Dimensions Symbol e x y A G Description Lead pitch Pad width Pad length. See Note. Typical Dimension 0.5 mm 0.25 mm 2.0 mm 7.75 mm 9.0 mm
Note: The y dimension has been elongated to allow for hand soldering and reworking. Production assembly may allow this dimension to be reduced as long as the G dimension is maintained.
102
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78M6612 Data Sheet
6.2
68-Pin QFN Package
6.2.1 Pinout
E_TCLK/SEG33
SEG41/DIO21
E_RST/SEG32
RX1/DIO1
V3P3A
GNDD
GNDD
TEST
XIN
VREF
VB
GNDD E_RXTX/SEG38 TX1/DIO2 TMUXOUT DIO3 TX0 SEG3 V3P3D CKTEST/SEG19 V3P3SYS SEG4 SEG5 SEG37/DIO17 COM0 COM1 COM2 COM3
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 50 49 48 47 46 45
VA
V1
IA
IB
GNDA
XOUT
RESET V2P5 VBAT RX0 SEG40/DIO20 SEG31/DIO11 SEG30/DIO10 SEG29/DIO9 SEG28/DIO8 SEG27/DIO7 SEG26/DIO6 SEG25/DIO5 SEG24/DIO4 ICE_E SEG18 SEG17 SEG16
TERIDIAN 78M6612-IM
44 43 42 41 40 39 38 37 36
35 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SEG10
SEG11
SEG12
SEG13
SEG14
SEG34/DIO14
SEG35/DIO15
SEG36/DIO16
SEG39/DIO19
Figure 43: 68-Pin QFN Pinout
Rev. 1.2
SEG15
SEG0
SEG1
SEG2
SEG6
SEG7
SEG8
SEG9
103
78M6612 Data Sheet
DS_6612_001
6.2.2 Package Outline
0.850
Dimensions (in mm): *) Pin length is nominally 0.4mm (min. 0.3 mm, max 0.4 mm). **) Exposed pad is internally connected to GNDD.
104
Rev. 1.2
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78M6612 Data Sheet
6.2.3 Recommended PCB Land Pattern for the QFN-68 Package
Recommended PCB Land Pattern Dimensions Symbol e x y d A G Description Lead pitch Pad width Pad length. See Note 3. See Note 1. Typical Dimension 0.4 mm 0.23 mm 0.8 mm 6.3 mm 6.63 mm 7.2 mm
Note 1: Do not place unmasked vias in region denoted by dimension d. Note 2: Soldering of bottom internal pad is not required for proper operation. Note 3: The y dimension has been elongated to allow for hand soldering and reworking. Production assembly may allow this dimension to be reduced as long as the G dimension is maintained.
Rev. 1.2
105
78M6612 Data Sheet
DS_6612_001
7 Pin Descriptions
7.1 Power/Ground Pins
Type P P P P Circuit - - - - Description Analog ground: This pin should be connected directly to the ground plane. Digital ground: This pin should be connected directly to the ground plane. Analog power supply: A 3.3V power supply should be connected to this pin, must be the same voltage as V3P3SYS. System 3.3 V supply. This pin should be connected to a 3.3 V power supply. Auxiliary voltage output of the chip, controlled by the internal 3.3 V selection switch. In mission mode, this pin is internally connected to V3P3SYS. In BROWNOUT mode, it is internally connected to VBAT. This pin is floating in LCD and sleep mode. Battery backup power supply. A battery or super-capacitor is to be connected between VBAT and GNDD. If no battery is used, connect VBAT to V3P3SYS. Output of the internal 2.5 V regulator. A 0.1 F capacitor to GNDA should be connected to this pin. Name GNDA GNDD V3P3A V3P3SYS
V3P3D
O
13
VBAT V2P5
P O
12 10
7.2
Analog Pins
Type I Circuit 6 Description Line Current Sense Inputs: These pins are voltage inputs to the internal A/D converter. Typically, they are connected to the outputs of current sensors. Unused pins must be connected to V3P3A. Line Voltage Sense Inputs: These pins are voltage inputs to the internal A/D converter. Typically, they are connected to the outputs of resistor dividers. Unused pins must be connected to V3P3A or tied to the voltage sense input that is in use. Comparator Input: This pin is a voltage input to the internal power-fail comparator. The input voltage is compared to the internal BIAS voltage (1.6 V). If the input voltage is above VBIAS, the comparator output will be high (1). If the comparator output is lower, a voltage fault will occur and the chip will be forced to battery mode. Voltage Reference for the ADC. This pin is normally disabled by setting the VREF_CAL bit in the I/O RAM and can then be left unconnected. If enabled, a 0.1 F capacitor to GNDA should be connected. Crystal Inputs: A 32 kHz crystal should be connected across these pins. Typically, a 27 pF capacitor is also connected from each pin to GNDA. It is important to minimize the capacitance between these pins. See the crystal manufacturer datasheet for details.
Name IA, IB
VA, VB
I
6
V1
I
7
VREF
O
9
XIN XOUT
I
8
Pin types: P = Power, O = Output, I = Input, I/O = Input/Output The circuit number denotes the equivalent circuit, as specified under "I/O Equivalent Circuits".
106
Rev. 1.2
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78M6612 Data Sheet
7.3
Digital Pins
Type O Circuit 5 Description
LCD common outputs: These four pins provide the select signals for the LCD display. Dedicated LCD segment output pins. SEG 14 and SEG15 are only available on the 68-pin package. Multi-use pins, configurable as either LCD SEG driver or DIO. (DIO4 = SCK, DIO5 = SDA when configured as EEPROM interface, WPULSE = DIO6, VARPULSE = DIO7 when configured as pulse outputs). If unused, these pins must be configured as DIOs and set to outputs by the firmware. Multi-use pins, configurable as either LCD SEG driver or DIO. If unused, these pins must be configured as DIOs and set to outputs by the firmware. Multi-use pins, configurable as LCD driver or DIO (QFN 68 package only). If unused, this pin must be configured as a DIO and set to an output by the firmware. Multi-use pins, configurable as either emulator port pins (when ICE_E pulled high) or LCD SEG drivers (when ICE_E tied to GND). ICE enable. When zero, E_RST, E_TCLK, and E_RXTX become SEG32, SEG33, and SEG38 respectively. For production units, this pin should be pulled to GND to disable the emulator port. This pin should be brought out to the programming interface in order to create a way for reprogramming parts that have the SECURE bit set. Multi-use pin, configurable as either Clock PLL output or LCD segment driver. Can be enabled and disabled by CKOUT_E[1:0]. Digital output test multiplexer. Controlled by TMUX[4:0]. Multi-use pin, configurable as UART1 Input or general DIO. When configured as RX1, this pin can optionally receive a signal from an external photo-detector used in an IR serial interface. If unused, this pin must be terminated to V3P3D or GNDD, or configured as a DIO and set to an output by the firmware. Multi-use pin, configurable as a transmit output from UART1 (or optionally an Optical LED Transmit Output), WPULSE, RPULSE, or general DIO. When configured as TX1, this pin is capable of directly driving an LED for transmitting data in an IR serial interface. If unused, this pin must be left open, or configured as a DIO and set to an output by the firmware. DIO pin (QFN 68 package only) This input pin resets the chip into a known state. For normal operation, this pin is connected to GNDD. To reset the chip, this pin should be pulled high. No external reset circuitry is necessary. Direct connect to ground in normal operation. UART input. If unused, this pin must be terminated to V3P3D or GNDD. UART output. Enables Production Test. Must be grounded in normal operation.
Name COM3, COM2, COM1, COM0 SEG0...SEG18 SEG24/DIO4... SEG31/DIO11 SEG34/DIO14 ... SEG37/DIO17, SEG39/DIO19, SEG40/DIO20 SEG41/DIO21 E_RXTX/SEG38 E_RST/SEG32 E_TCLK/SEG33
O
5
I/O
3, 4, 5
I/O
3, 4, 5
I/O I/O O
3, 4, 5 1, 4, 5 4, 5
ICE_E
I
2
CKTEST/SEG19 TMUXOUT
O O
4, 5 4
RX1/DIO1
I/O
3, 4, 7
TX1/DIO2
I/O
3, 4
DIO3 RESET RX0 TX0 TEST
I/O I I O I
3, 4 3 3 4 7
Pin types: P = Power, O = Output, I = Input, I/O = Input/Output The circuit number denotes the equivalent circuit, as specified on the following page. Rev. 1.2 107
78M6612 Data Sheet
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8 I/O Equivalent Circuits
V3P3D V3P3D V3P3A 110K Digital Input Pin GNDD GNDD Digital Input Equivalent Circuit Type 1: Standard Digital Input or pin configured as DIO Input with Internal Pull-Up V3P3D LCD Output Equivalent Circuit Type 5: LCD SEG or pin configured as LCD SEG GNDA VREF Equivalent Circuit Type 9: VREF CMOS Input LCD Driver LCD SEG Output Pin from internal reference VREF Pin
V3P3A V3P3D Digital Input Pin 110K GNDD GNDD GNDA Digital Input Type 2: Pin configured as DIO Input with Internal Pull-Down V3P3D V3P3A Digital Input Pin GNDD GNDA Digital Input Type 3: Standard Digital Input or pin configured as DIO Input V3P3D V3P3D 10 CMOS Output Digital Output Pin GNDD GNDD Digital Output Equivalent Circuit Type 4: Standard Digital Output or pin configured as DIO Output GNDD Oscillator Equivalent Circuit Type 8: Oscillator I/O from V3P3SYS Oscillator Pin To Oscillator 40 from VBAT V3P3D Equivalent Circuit Type 13: V3P3D V3P3D Pin Comparator Input Equivalent Circuit Type 7: Comparator Input GNDD VBAT Equivalent Circuit Type 12: VBAT Power CMOS Input Analog Input Equivalent Circuit Type 6: ADC Input GNDD V2P5 Equivalent Circuit Type 10: V2P5 CMOS Input
Analog Input Pin
To MUX
from internal reference
V2P5 Pin
Comparator Input Pin
To Comparator
VBAT Pin
Power Down Circuits
108
Rev. 1.2
DS_6612_001
78M6612 Data Sheet
9 Ordering Information
Part 78M6612 78M6612 78M6612 78M6612 78M6612 78M6612 78M6612 78M6612 Part Description (Package, accuracy) 64-pin LQFP, 0.5% 64-pin LQFP, 0.5% 64-pin LQFP, 0.5% 64-pin LQFP, 0.5% 68-pin QFN, 0.5% 68-pin QFN, 0.5% 68-pin QFN, 0.5% 68-pin QFN, 0.5% Flash Memory Size 32KB 32KB 32KB 32KB 32KB 32KB 32KB 32KB Packaging Bulk Tape & Reel Programmed, Bulk Programmed, Tape & Reel Bulk Tape & Reel Programmed, Bulk Programmed, Tape & Reel Ordering Number 78M6612-IGT/F 78M6612-IGTR/F 78M6612-IGT/F/P 78M6612-IGTR/F/P 78M6612-IM/F 78M6612-IMR/F 78M6612-IM/F/P 78M6612-IMR/F/P Package Marking 78M6612-IGT 78M6612-IGT 78M6612-IGT 78M6612-IGT 78M6612-IM 78M6612-IM 78M6612-IM 78M6612-IM
10 Related Documentation
The following documents applicable to the 78M6612 are available from Teridian Semiconductor Corporation: 78M6612 OMU Demo Unit User's Manual 78M6612_OMU Firmware Description Document 78M6612_ACPMON Demo Board User Manual 78M6612_ACPMON Firmware Description Document 78M6612 Firmware Developer's Manual
11 Contact Information
For more information about Teridian Semiconductor products or to check the availability of the 78M6612, contact us at: 6440 Oak Canyon Road Suite 100 Irvine, CA 92618-5201 Telephone: (714) 508-8800 FAX: (714) 508-8878 Email: omu.support@teridian.com For a complete list of worldwide sales offices, go to http://www.teridian.com.
Rev. 1.2
109
78M6612 Data Sheet
DS_6612_001
Revision History
Revision 1.0 1.1 1.2 Date 4/1/2009 5/6/2009 6/11/2009 Description First publication. Replaced Figure 39 with improved performance data. Miscellaneous editorial corrections. In Section 4.4.1, changed "CE6612_OMU_S2_A01_V1_0" to "CE6612_OMU_S2_A01_V1_2". In Section 4.4.6, changed "I0_SHUNT" to "I1_SHUNT" and "I1_SHUNT" to "I2_SHUNT". Also changed "W0SUM_X" to "W1SUM_X" and "W1SUM_X" to "W2SUM_X". In Section 4.4.7.1, changed "W0SUM_X" to "W1SUM_X" and "W1SUM_X" to "W2SUM_X". Also changed "VAR0SUM_X" to "VAR1SUM_X" and "VAR1SUM_X" to "VAR2SUM_X". In Section 4.4.7.2, changed "I0SQSUM_X" to "I1SQSUM_X" and "I1SQSUM_X" to "I2SQSUM_X". Changed the CE Address of WSUM_ACCUM from "0x7D" to "0x1B". Added CE Address 0x7C, V3SQSUM_X. Deleted CE Address 0x7E, VSUM_ACCUM. In Section 4.4.7.3, changed the CE Address for GAIN_ADJ from 0x18 to 0x19. In Section 4.4.7.6, changed "element 0" to "element 1" and "element 1" to "element 2". Changed "element A" to "element 1" and "element B" to "element 2". Also changed "I0SQSUM" to "I1SQSUM" and "I1SQSUM" to "I2SQSUM". In Figure 43, changed pin 65 from "PB" to "GNDD". In Section 7.3, changed "CKOUT_EN" to "CKOUT_E[1:0]".
(c) 2009 Teridian Semiconductor Corporation. All rights reserved. Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Simplifying System Integration is a trademark of Teridian Semiconductor Corporation. MicroDAA is a registered trademark of Teridian Semiconductor Corporation. All other trademarks are the property of their respective owners. Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly contained in the Company's warranty detailed in the Teridian Semiconductor Corporation standard Terms and Conditions. The company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice and does not make any commitment to update the information contained herein. Accordingly, the reader is cautioned to verify that this document is current by comparing it to the latest version on http://www.teridian.com or by checking with your sales representative. 110 Rev. 1.2
DS_6612_001
78M6612 Data Sheet
Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com
Rev. 1.2
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